root / proj / libs / uart / src / uart.c @ 354
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1 | 235 | up20180642 | #include <lcom/lcf.h> |
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2 | |||
3 | #include "uart.h" |
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4 | |||
5 | 275 | up20180642 | #include "queue.h" |
6 | 235 | up20180642 | #include "errors.h" |
7 | |||
8 | 249 | up20180642 | #define UART_BITRATE 115200 |
9 | #define UART_WAIT 20 //microseconds |
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10 | 241 | up20180642 | |
11 | 249 | up20180642 | #define UART_RBR 0 |
12 | #define UART_THR 0 |
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13 | #define UART_IER 1 |
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14 | #define UART_IIR 2 |
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15 | #define UART_FCR 2 |
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16 | #define UART_LCR 3 |
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17 | #define UART_MCR 4 |
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18 | #define UART_LSR 5 |
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19 | #define UART_MSR 6 |
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20 | #define UART_SR 7 |
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21 | 241 | up20180642 | |
22 | 249 | up20180642 | #define UART_DLL 0 |
23 | #define UART_DLM 1 |
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24 | 241 | up20180642 | |
25 | 249 | up20180642 | /// LCR
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26 | 277 | up20180642 | #define UART_BITS_PER_CHAR_POS 0 |
27 | 249 | up20180642 | #define UART_STOP_BITS_POS 2 |
28 | #define UART_PARITY_POS 3 |
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29 | #define UART_BREAK_CONTROL_POS 6 |
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30 | #define UART_DLAB_POS 7 |
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31 | 241 | up20180642 | |
32 | 249 | up20180642 | #define UART_BITS_PER_CHAR (BIT(0) | BIT(1)) |
33 | #define UART_STOP_BITS (BIT(2)) |
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34 | #define UART_PARITY (BIT(3) | BIT(4) | BIT(5)) |
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35 | #define UART_BREAK_CONTROL (BIT(6)) |
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36 | #define UART_DLAB (BIT(7)) |
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37 | 241 | up20180642 | |
38 | 249 | up20180642 | #define UART_GET_BITS_PER_CHAR(n) (((n)&UART_BITS_PER_CHAR) + 5) |
39 | #define UART_GET_STOP_BITS(n) (((n)&UART_STOP_BITS)? 2 : 1) |
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40 | #define UART_GET_PARITY(n) (((n)&UART_PARITY )>>UART_PARITY_POS )
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41 | #define UART_GET_BREAK_CONTROL(n) (((n)&UART_BREAK_CONTROL)>>UART_BREAK_CONTROL_POS)
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42 | #define UART_GET_DLAB(n) (((n)&UART_DLAB )>>UART_DLAB_POS )
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43 | #define UART_GET_DIV_LATCH(m,l) ((m)<<8 | (l)) |
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44 | #define UART_GET_DLL(n) ((n)&0xFF) |
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45 | #define UART_GET_DLM(n) (((n)>>8)&0xFF) |
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46 | 242 | up20180642 | |
47 | 249 | up20180642 | /// IER
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48 | 252 | up20180642 | #define UART_INT_EN_RX_POS 0 |
49 | #define UART_INT_EN_TX_POS 1 |
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50 | 249 | up20180642 | #define UART_INT_EN_RECEIVER_LINE_STAT_POS 2 |
51 | #define UART_INT_EN_MODEM_STAT_POS 3 |
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52 | 242 | up20180642 | |
53 | 252 | up20180642 | #define UART_INT_EN_RX (BIT(0)) |
54 | #define UART_INT_EN_TX (BIT(1)) |
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55 | 249 | up20180642 | #define UART_INT_EN_RECEIVER_LINE_STAT (BIT(2)) |
56 | #define UART_INT_EN_MODEM_STAT (BIT(3)) |
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57 | 242 | up20180642 | |
58 | 252 | up20180642 | #define UART_GET_INT_EN_RX(n) (((n)&UART_INT_EN_RX )>>UART_INT_EN_RX_POS )
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59 | #define UART_GET_INT_EN_TX(n) (((n)&UART_INT_EN_TX )>>UART_INT_EN_TX_POS )
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60 | #define UART_GET_INT_EN_RECEIVER_LINE_STAT(n) (((n)&UART_INT_EN_RECEIVER_LINE_STAT)>>UART_INT_EN_RECEIVER_LINE_STAT_POS)
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61 | #define UART_GET_INT_EN_MODEM_STAT(n) (((n)&UART_INT_EN_MODEM_STAT )>>UART_INT_EN_MODEM_STAT_POS )
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62 | 249 | up20180642 | |
63 | /// LSR
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64 | #define UART_RECEIVER_READY_POS 0 |
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65 | 261 | up20180642 | #define UART_OVERRUN_ERROR_POS 1 |
66 | #define UART_PARITY_ERROR_POS 2 |
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67 | #define UART_FRAMING_ERROR_POS 3 |
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68 | 249 | up20180642 | #define UART_TRANSMITTER_EMPTY_POS 5 |
69 | |||
70 | #define UART_RECEIVER_READY (BIT(0)) |
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71 | 261 | up20180642 | #define UART_OVERRUN_ERROR (BIT(1)) |
72 | #define UART_PARITY_ERROR (BIT(2)) |
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73 | #define UART_FRAMING_ERROR (BIT(3)) |
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74 | 249 | up20180642 | #define UART_TRANSMITTER_EMPTY (BIT(5)) |
75 | |||
76 | #define UART_GET_RECEIVER_READY(n) (((n)&UART_RECEIVER_READY )>>UART_RECEIVER_READY_POS )
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77 | 261 | up20180642 | #define UART_GET_OVERRUN_ERROR (((n)&UART_OVERRUN_ERROR )>>UART_OVERRUN_ERROR_POS )
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78 | #define UART_GET_PARITY_ERROR (((n)&UART_PARITY_ERROR )>>UART_PARITY_ERROR_POS )
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79 | #define UART_GET_FRAMING_ERROR (((n)&UART_FRAMING_ERROR )>>UART_FRAMING_ERROR_POS )
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80 | 249 | up20180642 | #define UART_GET_TRANSMITTER_EMPTY(n) (((n)&UART_TRANSMITTER_EMPTY )>>UART_TRANSMITTER_EMPTY_POS )
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81 | |||
82 | 275 | up20180642 | /// IIR
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83 | 277 | up20180642 | #define UART_INT_PEND_POS 1 |
84 | |||
85 | #define UART_INT_PEND (BIT(3)|BIT(2)|BIT(1)) |
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86 | |||
87 | 275 | up20180642 | #define UART_GET_IF_INT_PEND(n) (!((n)&1)) |
88 | 277 | up20180642 | typedef enum { |
89 | uart_int_receiver_line_stat = ( BIT(1) | BIT(0)), |
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90 | uart_int_rx = ( BIT(1) ),
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91 | uart_int_char_timeout_fifo = (BIT(2) | BIT(1) ), |
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92 | uart_int_tx = ( BIT(0)),
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93 | uart_int_modem_stat = (0)
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94 | } uart_int_code; |
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95 | #define UART_GET_INT_PEND(n) ((uart_int_code)(((n)&UART_INT_PEND)>>UART_INT_PEND_POS))
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96 | 275 | up20180642 | |
97 | 263 | up20180642 | int (subscribe_uart_interrupt)(uint8_t interrupt_bit, int *interrupt_id) { |
98 | if (interrupt_id == NULL) return 1; |
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99 | *interrupt_id = interrupt_bit; |
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100 | return (sys_irqsetpolicy(COM1_IRQ, IRQ_REENABLE | IRQ_EXCLUSIVE, interrupt_id));
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101 | } |
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102 | |||
103 | 252 | up20180642 | static void uart_parse_config(uart_config *config){ |
104 | /// LCR
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105 | config->bits_per_char = UART_GET_BITS_PER_CHAR (config->lcr); |
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106 | config->stop_bits = UART_GET_STOP_BITS (config->lcr); |
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107 | config->parity = UART_GET_PARITY (config->lcr); if((config->parity & BIT(0)) == 0) config->parity = uart_parity_none; |
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108 | config->break_control = UART_GET_BREAK_CONTROL (config->lcr); |
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109 | config->dlab = UART_GET_DLAB (config->lcr); |
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110 | /// IER
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111 | config->received_data_int = UART_GET_INT_EN_RX (config->ier); |
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112 | config->transmitter_empty_int = UART_GET_INT_EN_TX (config->ier); |
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113 | config->receiver_line_stat_int = UART_GET_INT_EN_RECEIVER_LINE_STAT(config->ier); |
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114 | config->modem_stat_int = UART_GET_INT_EN_MODEM_STAT (config->ier); |
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115 | /// DIV LATCH
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116 | 324 | up20180642 | config->divisor_latch = (uint16_t)UART_GET_DIV_LATCH(config->dlm, config->dll); |
117 | 252 | up20180642 | } |
118 | |||
119 | static int uart_get_lcr(int base_addr, uint8_t *p){ |
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120 | return util_sys_inb(base_addr+UART_LCR, p);
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121 | } |
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122 | static int uart_set_lcr(int base_addr, uint8_t config){ |
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123 | if(sys_outb(base_addr+UART_LCR, config)) return WRITE_ERROR; |
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124 | return SUCCESS;
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125 | } |
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126 | static int uart_get_lsr(int base_addr, uint8_t *p){ |
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127 | return util_sys_inb(base_addr+UART_LSR, p);
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128 | } |
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129 | 275 | up20180642 | static int uart_get_iir(int base_addr, uint8_t *p){ |
130 | return util_sys_inb(base_addr+UART_IIR, p);
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131 | } |
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132 | 252 | up20180642 | |
133 | static int uart_enable_divisor_latch(int base_addr){ |
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134 | int ret = SUCCESS;
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135 | uint8_t conf; if((ret = uart_get_lcr(base_addr, &conf))) return ret; |
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136 | return uart_set_lcr(base_addr, conf | UART_DLAB);
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137 | } |
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138 | static int uart_disable_divisor_latch(int base_addr){ |
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139 | int ret = SUCCESS;
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140 | uint8_t conf; if((ret = uart_get_lcr(base_addr, &conf))) return ret; |
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141 | return uart_set_lcr(base_addr, conf & (~UART_DLAB));
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142 | } |
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143 | |||
144 | static int uart_get_ier(int base_addr, uint8_t *p){ |
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145 | int ret;
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146 | if((ret = uart_disable_divisor_latch(base_addr))) return ret; |
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147 | return util_sys_inb(base_addr+UART_IER, p);
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148 | } |
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149 | static int uart_set_ier(int base_addr, uint8_t n){ |
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150 | int ret;
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151 | if((ret = uart_disable_divisor_latch(base_addr))) return ret; |
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152 | if(sys_outb(base_addr+UART_IER, n)) return WRITE_ERROR; |
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153 | return SUCCESS;
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154 | } |
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155 | |||
156 | 235 | up20180642 | int uart_get_config(int base_addr, uart_config *config){ |
157 | int ret = SUCCESS;
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158 | |||
159 | config->base_addr = base_addr; |
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160 | |||
161 | 252 | up20180642 | if((ret = uart_get_lcr(base_addr, &config->lcr))) return ret; |
162 | 235 | up20180642 | |
163 | 252 | up20180642 | if((ret = uart_get_ier(base_addr, &config->ier))) return ret; |
164 | 242 | up20180642 | |
165 | if((ret = uart_enable_divisor_latch (base_addr))) return ret; |
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166 | 235 | up20180642 | if((ret = util_sys_inb(base_addr+UART_DLL, &config->dll ))) return ret; |
167 | if((ret = util_sys_inb(base_addr+UART_DLM, &config->dlm ))) return ret; |
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168 | 242 | up20180642 | if((ret = uart_disable_divisor_latch(base_addr))) return ret; |
169 | 235 | up20180642 | |
170 | uart_parse_config(config); |
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171 | return ret;
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172 | } |
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173 | void uart_print_config(uart_config config){
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174 | 249 | up20180642 | |
175 | printf("%s configuration:\n", (config.base_addr == COM1_ADDR ? "COM1" : "COM2")); |
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176 | printf("\tLCR = 0x%X: %d bits per char\t %d stop bits\t", config.lcr, config.bits_per_char, config.stop_bits);
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177 | if((config.parity&BIT(0)) == 0) printf("NO parity\n"); |
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178 | 235 | up20180642 | else switch(config.parity){ |
179 | 324 | up20180642 | case uart_parity_none: printf("NO parity\n" ); break; |
180 | 249 | up20180642 | case uart_parity_odd : printf("ODD parity\n" ); break; |
181 | case uart_parity_even: printf("EVEN parity\n" ); break; |
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182 | 235 | up20180642 | case uart_parity_par1: printf("parity bit is 1\n"); break; |
183 | case uart_parity_par0: printf("parity bit is 0\n"); break; |
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184 | 324 | up20180642 | //default : printf("invalid\n" ); break;
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185 | 235 | up20180642 | } |
186 | 249 | up20180642 | printf("\tDLM = 0x%02X DLL=0x%02X: bitrate = %d bps\n", config.dlm, config.dll, UART_BITRATE/config.divisor_latch);
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187 | printf("\tIER = 0x%02X: Rx interrupts: %s\tTx interrupts: %s\n", config.ier,
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188 | (config.received_data_int ? "ENABLED":"DISABLED"), |
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189 | (config.transmitter_empty_int ? "ENABLED":"DISABLED")); |
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190 | 235 | up20180642 | } |
191 | |||
192 | int uart_set_bits_per_character(int base_addr, uint8_t bits_per_char){ |
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193 | if(bits_per_char < 5 || bits_per_char > 8) return INVALID_ARG; |
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194 | int ret = SUCCESS;
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195 | bits_per_char = (bits_per_char-5)&0x3; |
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196 | 252 | up20180642 | uint8_t conf; if((ret = uart_get_lcr(base_addr, &conf))) return ret; |
197 | 235 | up20180642 | conf = (conf & (~UART_BITS_PER_CHAR)) | bits_per_char; |
198 | 252 | up20180642 | return uart_set_lcr(base_addr, conf);
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199 | 235 | up20180642 | } |
200 | int uart_set_stop_bits(int base_addr, uint8_t stop){ |
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201 | if(stop != 1 && stop != 2) return INVALID_ARG; |
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202 | int ret = SUCCESS;
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203 | stop -= 1;
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204 | 324 | up20180642 | stop = (uint8_t)((stop&1)<<2); |
205 | 252 | up20180642 | uint8_t conf; if((ret = uart_get_lcr(base_addr, &conf))) return ret; |
206 | 235 | up20180642 | conf = (conf & (~UART_STOP_BITS)) | stop; |
207 | 252 | up20180642 | return uart_set_lcr(base_addr, conf);
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208 | 235 | up20180642 | } |
209 | int uart_set_parity(int base_addr, uart_parity par){ |
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210 | int ret = SUCCESS;
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211 | 324 | up20180642 | uint8_t parity = (uint8_t)(par << 3);
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212 | 252 | up20180642 | uint8_t conf; if((ret = uart_get_lcr(base_addr, &conf))) return ret; |
213 | 235 | up20180642 | conf = (conf & (~UART_PARITY)) | parity; |
214 | 252 | up20180642 | return uart_set_lcr(base_addr, conf);
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215 | 235 | up20180642 | } |
216 | 328 | up20180642 | int uart_set_bit_rate(int base_addr, uint32_t bit_rate){ |
217 | 235 | up20180642 | int ret = SUCCESS;
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218 | 324 | up20180642 | uint16_t latch = (uint16_t)(UART_BITRATE/bit_rate); |
219 | 241 | up20180642 | uint8_t dll = UART_GET_DLL(latch); |
220 | uint8_t dlm = UART_GET_DLM(latch); |
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221 | 235 | up20180642 | if((ret = uart_enable_divisor_latch(base_addr))) return ret; |
222 | if(sys_outb(base_addr+UART_DLL, dll)) return WRITE_ERROR; |
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223 | if(sys_outb(base_addr+UART_DLM, dlm)) return WRITE_ERROR; |
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224 | 249 | up20180642 | if((ret = uart_disable_divisor_latch(base_addr))) return ret; |
225 | 235 | up20180642 | return SUCCESS;
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226 | } |
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227 | 249 | up20180642 | |
228 | 252 | up20180642 | static int uart_get_char(int base_addr, uint8_t *p){ |
229 | 249 | up20180642 | int ret;
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230 | if((ret = uart_disable_divisor_latch(base_addr))) return ret; |
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231 | return util_sys_inb(base_addr+UART_RBR, p);
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232 | } |
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233 | 252 | up20180642 | static int uart_send_char(int base_addr, uint8_t c){ |
234 | 249 | up20180642 | int ret;
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235 | if((ret = uart_disable_divisor_latch(base_addr))) return ret; |
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236 | 252 | up20180642 | if(sys_outb(base_addr+UART_THR, c)) return WRITE_ERROR; |
237 | 249 | up20180642 | return SUCCESS;
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238 | } |
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239 | 252 | up20180642 | static int uart_receiver_ready(int base_addr){ |
240 | 249 | up20180642 | uint8_t lsr; |
241 | if(uart_get_lsr(base_addr, &lsr)) return false; |
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242 | return UART_GET_RECEIVER_READY(lsr);
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243 | } |
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244 | 252 | up20180642 | static int uart_transmitter_empty(int base_addr){ |
245 | 249 | up20180642 | uint8_t lsr; |
246 | if(uart_get_lsr(base_addr, &lsr)) return false; |
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247 | return UART_GET_TRANSMITTER_EMPTY(lsr);
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248 | } |
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249 | 252 | up20180642 | |
250 | int uart_enable_int_rx(int base_addr){ |
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251 | int ret;
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252 | uint8_t ier; |
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253 | if((ret = uart_get_ier(base_addr, &ier))) return ret; |
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254 | ier |= UART_INT_EN_RX; |
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255 | return uart_set_ier(base_addr, ier);
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256 | } |
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257 | int uart_disable_int_rx(int base_addr){ |
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258 | int ret;
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259 | uint8_t ier; |
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260 | if((ret = uart_get_ier(base_addr, &ier))) return ret; |
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261 | ier &= ~UART_INT_EN_RX; |
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262 | return uart_set_ier(base_addr, ier);
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263 | } |
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264 | int uart_enable_int_tx(int base_addr){ |
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265 | int ret;
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266 | uint8_t ier; |
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267 | if((ret = uart_get_ier(base_addr, &ier))) return ret; |
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268 | ier |= UART_INT_EN_TX; |
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269 | return uart_set_ier(base_addr, ier);
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270 | } |
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271 | int uart_disable_int_tx(int base_addr){ |
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272 | int ret;
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273 | uint8_t ier; |
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274 | if((ret = uart_get_ier(base_addr, &ier))) return ret; |
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275 | ier &= ~UART_INT_EN_TX; |
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276 | return uart_set_ier(base_addr, ier);
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277 | } |
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278 | |||
279 | 283 | up20180642 | /// NCTP
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280 | 261 | up20180642 | |
281 | 344 | up20180642 | //#define NCTP_START 0x80
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282 | //#define NCTP_END 0xFF
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283 | 261 | up20180642 | #define NCTP_OK 0xFF |
284 | #define NCTP_NOK 0x00 |
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285 | |||
286 | 324 | up20180642 | static queue_t *out = NULL; |
287 | static queue_t *in = NULL; |
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288 | static void (*process)(const uint8_t*, const size_t) = NULL; |
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289 | 261 | up20180642 | |
290 | 298 | up20180642 | int nctp_init(void){ |
291 | 275 | up20180642 | out = queue_ctor(); if(out == NULL) return NULL_PTR; |
292 | in = queue_ctor(); if(in == NULL) return NULL_PTR; |
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293 | 297 | up20180642 | return SUCCESS;
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294 | } |
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295 | 298 | up20180642 | int nctp_dump(void){ |
296 | int ret;
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297 | if((ret = nctp_free())) return ret; |
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298 | return nctp_init();
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299 | } |
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300 | 297 | up20180642 | int nctp_set_processor(void (*proc_func)(const uint8_t*, const size_t)){ |
301 | 287 | up20180642 | process = proc_func; |
302 | 275 | up20180642 | return SUCCESS;
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303 | 261 | up20180642 | } |
304 | 275 | up20180642 | int nctp_free(void){ |
305 | while(!queue_empty(out)){
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306 | free(queue_top(out)); |
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307 | queue_pop(out); |
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308 | 261 | up20180642 | } |
309 | 275 | up20180642 | while(!queue_empty(in)){
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310 | free(queue_top(in)); |
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311 | queue_pop(in); |
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312 | 261 | up20180642 | } |
313 | 275 | up20180642 | return SUCCESS;
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314 | 261 | up20180642 | } |
315 | |||
316 | 325 | up20180642 | int nctp_send(size_t num, const uint8_t *const *ptr, const size_t *const sz){ |
317 | 261 | up20180642 | int ret;
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318 | 344 | up20180642 | uint16_t sz_total = 0;{
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319 | for(size_t i = 0; i < num; ++i) |
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320 | sz_total += sz[i]; |
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321 | } |
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322 | 275 | up20180642 | uint8_t *tmp; |
323 | 344 | up20180642 | tmp = malloc(sizeof(uint8_t)); *tmp = *((uint8_t*)(&sz_total)+0); queue_push(out, tmp); |
324 | tmp = malloc(sizeof(uint8_t)); *tmp = *((uint8_t*)(&sz_total)+1); queue_push(out, tmp); |
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325 | 261 | up20180642 | for(size_t i = 0; i < num; ++i){ |
326 | 325 | up20180642 | const uint8_t *p = ptr[i]; const size_t s = sz[i]; |
327 | 275 | up20180642 | for(size_t j = 0; j < s; ++j, ++p){ |
328 | tmp = malloc(sizeof(uint8_t)); *tmp = *p; queue_push(out, tmp);
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329 | } |
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330 | 261 | up20180642 | } |
331 | 344 | up20180642 | |
332 | 275 | up20180642 | if(uart_transmitter_empty(COM1_ADDR)){
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333 | if((ret = uart_send_char(COM1_ADDR, *(uint8_t*)queue_top(out)))) return ret; |
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334 | queue_pop(out); |
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335 | } |
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336 | 249 | up20180642 | return SUCCESS;
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337 | } |
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338 | 275 | up20180642 | static int nctp_transmit(void){ |
339 | if(!queue_empty(out)){
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340 | int ret = uart_send_char(COM1_ADDR, *(uint8_t*)queue_top(out));
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341 | queue_pop(out); |
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342 | return ret;
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343 | }else return SUCCESS; |
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344 | 269 | up20180642 | } |
345 | 278 | up20180642 | |
346 | 287 | up20180642 | static void nctp_process_received(){ |
347 | 344 | up20180642 | uint16_t sz = 0;{
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348 | uint8_t sz0 = *(uint8_t*)queue_top(in); free(queue_top(in)); queue_pop(in); |
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349 | uint8_t sz1 = *(uint8_t*)queue_top(in); free(queue_top(in)); queue_pop(in); |
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350 | *((uint8_t*)(&sz)+0) = sz0;
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351 | *((uint8_t*)(&sz)+1) = sz1;
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352 | } |
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353 | uint8_t *p = malloc(sz*sizeof(uint8_t));
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354 | for(uint16_t i = 0; i < sz; ++i){ |
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355 | p[i] = *(uint8_t*)queue_top(in); |
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356 | 275 | up20180642 | free(queue_top(in)); queue_pop(in); |
357 | 344 | up20180642 | } |
358 | if(process != NULL) process(p, sz); |
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359 | 287 | up20180642 | free(p); |
360 | 275 | up20180642 | } |
361 | 344 | up20180642 | |
362 | static int num_bytes_to_receive = 0; |
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363 | static uint16_t szbytes_to_receive = 0; |
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364 | static uint8_t size0 = 0; |
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365 | 275 | up20180642 | static int nctp_receive(void){ |
366 | 249 | up20180642 | int ret;
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367 | 261 | up20180642 | uint8_t c; |
368 | 344 | up20180642 | int counter_to_process = 0; |
369 | |||
370 | 275 | up20180642 | while(uart_receiver_ready(COM1_ADDR)){
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371 | if((ret = uart_get_char(COM1_ADDR, &c))) return ret; |
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372 | uint8_t *tmp = malloc(sizeof(uint8_t)); *tmp = c;
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373 | 344 | up20180642 | |
374 | 275 | up20180642 | queue_push(in, tmp); |
375 | 344 | up20180642 | |
376 | if (szbytes_to_receive){ // gotta receive 2nd size byte and update num_bytes |
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377 | *((uint8_t*)(&num_bytes_to_receive)+0) = size0;
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378 | *((uint8_t*)(&num_bytes_to_receive)+1) = c;
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379 | szbytes_to_receive = 0;
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380 | } else if(num_bytes_to_receive > 0){ |
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381 | /* Now I know there are no more size bytes to receive.
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382 | * If there are normal bytes to receive*/
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383 | --num_bytes_to_receive; |
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384 | if(num_bytes_to_receive == 0) ++counter_to_process; |
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385 | } else {
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386 | /* Now I know I am not expecting anything.
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387 | * The fact I received something means it is the 1st size byte */
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388 | size0 = c; |
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389 | szbytes_to_receive = 1;
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390 | } |
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391 | 261 | up20180642 | } |
392 | 344 | up20180642 | while(counter_to_process-- > 0) nctp_process_received(); |
393 | 275 | up20180642 | return SUCCESS;
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394 | 249 | up20180642 | } |
395 | 275 | up20180642 | |
396 | 323 | up20180642 | static int nctp_ih_err = SUCCESS; |
397 | int (nctp_get_ih_error)(void){ return nctp_ih_err; } |
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398 | 275 | up20180642 | void nctp_ih(void){ |
399 | uint8_t iir; |
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400 | if((nctp_ih_err = uart_get_iir(COM1_ADDR, &iir))) return; |
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401 | if(UART_GET_IF_INT_PEND(iir)){
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402 | switch(UART_GET_INT_PEND(iir)){
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403 | 277 | up20180642 | case uart_int_rx: nctp_receive (); break; |
404 | case uart_int_tx: nctp_transmit(); break; |
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405 | 324 | up20180642 | case uart_int_receiver_line_stat: break; |
406 | case uart_int_modem_stat: break; |
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407 | case uart_int_char_timeout_fifo: break; |
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408 | //default: break;
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409 | 275 | up20180642 | } |
410 | } |
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411 | 269 | up20180642 | } |