root / proj / libs / uart / src / uart.c @ 346
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#include <lcom/lcf.h> |
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|
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#include "uart.h" |
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|
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#include "queue.h" |
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#include "errors.h" |
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|
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#define UART_BITRATE 115200 |
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#define UART_WAIT 20 //microseconds |
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|
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#define UART_RBR 0 |
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#define UART_THR 0 |
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#define UART_IER 1 |
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#define UART_IIR 2 |
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#define UART_FCR 2 |
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#define UART_LCR 3 |
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#define UART_MCR 4 |
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#define UART_LSR 5 |
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#define UART_MSR 6 |
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#define UART_SR 7 |
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|
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#define UART_DLL 0 |
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#define UART_DLM 1 |
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|
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/// LCR
|
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#define UART_BITS_PER_CHAR_POS 0 |
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#define UART_STOP_BITS_POS 2 |
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#define UART_PARITY_POS 3 |
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#define UART_BREAK_CONTROL_POS 6 |
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#define UART_DLAB_POS 7 |
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|
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#define UART_BITS_PER_CHAR (BIT(0) | BIT(1)) |
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#define UART_STOP_BITS (BIT(2)) |
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#define UART_PARITY (BIT(3) | BIT(4) | BIT(5)) |
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#define UART_BREAK_CONTROL (BIT(6)) |
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#define UART_DLAB (BIT(7)) |
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|
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#define UART_GET_BITS_PER_CHAR(n) (((n)&UART_BITS_PER_CHAR) + 5) |
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#define UART_GET_STOP_BITS(n) (((n)&UART_STOP_BITS)? 2 : 1) |
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#define UART_GET_PARITY(n) (((n)&UART_PARITY )>>UART_PARITY_POS )
|
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#define UART_GET_BREAK_CONTROL(n) (((n)&UART_BREAK_CONTROL)>>UART_BREAK_CONTROL_POS)
|
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#define UART_GET_DLAB(n) (((n)&UART_DLAB )>>UART_DLAB_POS )
|
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#define UART_GET_DIV_LATCH(m,l) ((m)<<8 | (l)) |
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#define UART_GET_DLL(n) ((n)&0xFF) |
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#define UART_GET_DLM(n) (((n)>>8)&0xFF) |
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|
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/// IER
|
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#define UART_INT_EN_RX_POS 0 |
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#define UART_INT_EN_TX_POS 1 |
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#define UART_INT_EN_RECEIVER_LINE_STAT_POS 2 |
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#define UART_INT_EN_MODEM_STAT_POS 3 |
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|
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#define UART_INT_EN_RX (BIT(0)) |
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#define UART_INT_EN_TX (BIT(1)) |
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#define UART_INT_EN_RECEIVER_LINE_STAT (BIT(2)) |
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#define UART_INT_EN_MODEM_STAT (BIT(3)) |
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|
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#define UART_GET_INT_EN_RX(n) (((n)&UART_INT_EN_RX )>>UART_INT_EN_RX_POS )
|
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#define UART_GET_INT_EN_TX(n) (((n)&UART_INT_EN_TX )>>UART_INT_EN_TX_POS )
|
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#define UART_GET_INT_EN_RECEIVER_LINE_STAT(n) (((n)&UART_INT_EN_RECEIVER_LINE_STAT)>>UART_INT_EN_RECEIVER_LINE_STAT_POS)
|
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#define UART_GET_INT_EN_MODEM_STAT(n) (((n)&UART_INT_EN_MODEM_STAT )>>UART_INT_EN_MODEM_STAT_POS )
|
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|
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/// LSR
|
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#define UART_RECEIVER_READY_POS 0 |
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#define UART_OVERRUN_ERROR_POS 1 |
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#define UART_PARITY_ERROR_POS 2 |
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#define UART_FRAMING_ERROR_POS 3 |
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#define UART_TRANSMITTER_EMPTY_POS 5 |
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|
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#define UART_RECEIVER_READY (BIT(0)) |
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#define UART_OVERRUN_ERROR (BIT(1)) |
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#define UART_PARITY_ERROR (BIT(2)) |
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#define UART_FRAMING_ERROR (BIT(3)) |
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#define UART_TRANSMITTER_EMPTY (BIT(5)) |
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|
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#define UART_GET_RECEIVER_READY(n) (((n)&UART_RECEIVER_READY )>>UART_RECEIVER_READY_POS )
|
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#define UART_GET_OVERRUN_ERROR (((n)&UART_OVERRUN_ERROR )>>UART_OVERRUN_ERROR_POS )
|
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#define UART_GET_PARITY_ERROR (((n)&UART_PARITY_ERROR )>>UART_PARITY_ERROR_POS )
|
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#define UART_GET_FRAMING_ERROR (((n)&UART_FRAMING_ERROR )>>UART_FRAMING_ERROR_POS )
|
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#define UART_GET_TRANSMITTER_EMPTY(n) (((n)&UART_TRANSMITTER_EMPTY )>>UART_TRANSMITTER_EMPTY_POS )
|
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|
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/// IIR
|
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#define UART_INT_PEND_POS 1 |
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|
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#define UART_INT_PEND (BIT(3)|BIT(2)|BIT(1)) |
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|
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#define UART_GET_IF_INT_PEND(n) (!((n)&1)) |
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typedef enum { |
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uart_int_receiver_line_stat = ( BIT(1) | BIT(0)), |
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uart_int_rx = ( BIT(1) ),
|
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uart_int_char_timeout_fifo = (BIT(2) | BIT(1) ), |
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uart_int_tx = ( BIT(0)),
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uart_int_modem_stat = (0)
|
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} uart_int_code; |
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#define UART_GET_INT_PEND(n) ((uart_int_code)(((n)&UART_INT_PEND)>>UART_INT_PEND_POS))
|
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|
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int (subscribe_uart_interrupt)(uint8_t interrupt_bit, int *interrupt_id) { |
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if (interrupt_id == NULL) return 1; |
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*interrupt_id = interrupt_bit; |
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return (sys_irqsetpolicy(COM1_IRQ, IRQ_REENABLE | IRQ_EXCLUSIVE, interrupt_id));
|
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} |
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|
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static void uart_parse_config(uart_config *config){ |
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/// LCR
|
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config->bits_per_char = UART_GET_BITS_PER_CHAR (config->lcr); |
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config->stop_bits = UART_GET_STOP_BITS (config->lcr); |
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config->parity = UART_GET_PARITY (config->lcr); if((config->parity & BIT(0)) == 0) config->parity = uart_parity_none; |
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config->break_control = UART_GET_BREAK_CONTROL (config->lcr); |
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config->dlab = UART_GET_DLAB (config->lcr); |
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/// IER
|
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config->received_data_int = UART_GET_INT_EN_RX (config->ier); |
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config->transmitter_empty_int = UART_GET_INT_EN_TX (config->ier); |
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config->receiver_line_stat_int = UART_GET_INT_EN_RECEIVER_LINE_STAT(config->ier); |
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config->modem_stat_int = UART_GET_INT_EN_MODEM_STAT (config->ier); |
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/// DIV LATCH
|
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config->divisor_latch = (uint16_t)UART_GET_DIV_LATCH(config->dlm, config->dll); |
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} |
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|
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static int uart_get_lcr(int base_addr, uint8_t *p){ |
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return util_sys_inb(base_addr+UART_LCR, p);
|
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} |
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static int uart_set_lcr(int base_addr, uint8_t config){ |
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if(sys_outb(base_addr+UART_LCR, config)) return WRITE_ERROR; |
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return SUCCESS;
|
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} |
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static int uart_get_lsr(int base_addr, uint8_t *p){ |
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return util_sys_inb(base_addr+UART_LSR, p);
|
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} |
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static int uart_get_iir(int base_addr, uint8_t *p){ |
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return util_sys_inb(base_addr+UART_IIR, p);
|
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} |
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|
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static int uart_enable_divisor_latch(int base_addr){ |
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int ret = SUCCESS;
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uint8_t conf; if((ret = uart_get_lcr(base_addr, &conf))) return ret; |
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return uart_set_lcr(base_addr, conf | UART_DLAB);
|
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} |
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static int uart_disable_divisor_latch(int base_addr){ |
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int ret = SUCCESS;
|
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uint8_t conf; if((ret = uart_get_lcr(base_addr, &conf))) return ret; |
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return uart_set_lcr(base_addr, conf & (~UART_DLAB));
|
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} |
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|
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static int uart_get_ier(int base_addr, uint8_t *p){ |
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int ret;
|
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if((ret = uart_disable_divisor_latch(base_addr))) return ret; |
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return util_sys_inb(base_addr+UART_IER, p);
|
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} |
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static int uart_set_ier(int base_addr, uint8_t n){ |
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int ret;
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if((ret = uart_disable_divisor_latch(base_addr))) return ret; |
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if(sys_outb(base_addr+UART_IER, n)) return WRITE_ERROR; |
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return SUCCESS;
|
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} |
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|
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int uart_get_config(int base_addr, uart_config *config){ |
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int ret = SUCCESS;
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|
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config->base_addr = base_addr; |
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|
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if((ret = uart_get_lcr(base_addr, &config->lcr))) return ret; |
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|
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if((ret = uart_get_ier(base_addr, &config->ier))) return ret; |
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|
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if((ret = uart_enable_divisor_latch (base_addr))) return ret; |
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if((ret = util_sys_inb(base_addr+UART_DLL, &config->dll ))) return ret; |
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if((ret = util_sys_inb(base_addr+UART_DLM, &config->dlm ))) return ret; |
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if((ret = uart_disable_divisor_latch(base_addr))) return ret; |
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|
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uart_parse_config(config); |
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return ret;
|
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} |
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void uart_print_config(uart_config config){
|
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|
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printf("%s configuration:\n", (config.base_addr == COM1_ADDR ? "COM1" : "COM2")); |
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printf("\tLCR = 0x%X: %d bits per char\t %d stop bits\t", config.lcr, config.bits_per_char, config.stop_bits);
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if((config.parity&BIT(0)) == 0) printf("NO parity\n"); |
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else switch(config.parity){ |
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case uart_parity_none: printf("NO parity\n" ); break; |
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case uart_parity_odd : printf("ODD parity\n" ); break; |
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case uart_parity_even: printf("EVEN parity\n" ); break; |
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case uart_parity_par1: printf("parity bit is 1\n"); break; |
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case uart_parity_par0: printf("parity bit is 0\n"); break; |
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//default : printf("invalid\n" ); break;
|
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} |
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printf("\tDLM = 0x%02X DLL=0x%02X: bitrate = %d bps\n", config.dlm, config.dll, UART_BITRATE/config.divisor_latch);
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printf("\tIER = 0x%02X: Rx interrupts: %s\tTx interrupts: %s\n", config.ier,
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(config.received_data_int ? "ENABLED":"DISABLED"), |
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(config.transmitter_empty_int ? "ENABLED":"DISABLED")); |
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} |
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|
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int uart_set_bits_per_character(int base_addr, uint8_t bits_per_char){ |
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if(bits_per_char < 5 || bits_per_char > 8) return INVALID_ARG; |
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int ret = SUCCESS;
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bits_per_char = (bits_per_char-5)&0x3; |
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uint8_t conf; if((ret = uart_get_lcr(base_addr, &conf))) return ret; |
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conf = (conf & (~UART_BITS_PER_CHAR)) | bits_per_char; |
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return uart_set_lcr(base_addr, conf);
|
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} |
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int uart_set_stop_bits(int base_addr, uint8_t stop){ |
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if(stop != 1 && stop != 2) return INVALID_ARG; |
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int ret = SUCCESS;
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stop -= 1;
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stop = (uint8_t)((stop&1)<<2); |
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uint8_t conf; if((ret = uart_get_lcr(base_addr, &conf))) return ret; |
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conf = (conf & (~UART_STOP_BITS)) | stop; |
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return uart_set_lcr(base_addr, conf);
|
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} |
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int uart_set_parity(int base_addr, uart_parity par){ |
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int ret = SUCCESS;
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uint8_t parity = (uint8_t)(par << 3);
|
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uint8_t conf; if((ret = uart_get_lcr(base_addr, &conf))) return ret; |
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conf = (conf & (~UART_PARITY)) | parity; |
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return uart_set_lcr(base_addr, conf);
|
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} |
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int uart_set_bit_rate(int base_addr, uint32_t bit_rate){ |
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int ret = SUCCESS;
|
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uint16_t latch = (uint16_t)(UART_BITRATE/bit_rate); |
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uint8_t dll = UART_GET_DLL(latch); |
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uint8_t dlm = UART_GET_DLM(latch); |
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if((ret = uart_enable_divisor_latch(base_addr))) return ret; |
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if(sys_outb(base_addr+UART_DLL, dll)) return WRITE_ERROR; |
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if(sys_outb(base_addr+UART_DLM, dlm)) return WRITE_ERROR; |
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if((ret = uart_disable_divisor_latch(base_addr))) return ret; |
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return SUCCESS;
|
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} |
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|
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static int uart_get_char(int base_addr, uint8_t *p){ |
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int ret;
|
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if((ret = uart_disable_divisor_latch(base_addr))) return ret; |
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return util_sys_inb(base_addr+UART_RBR, p);
|
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} |
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static int uart_send_char(int base_addr, uint8_t c){ |
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int ret;
|
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if((ret = uart_disable_divisor_latch(base_addr))) return ret; |
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if(sys_outb(base_addr+UART_THR, c)) return WRITE_ERROR; |
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return SUCCESS;
|
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} |
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static int uart_receiver_ready(int base_addr){ |
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uint8_t lsr; |
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if(uart_get_lsr(base_addr, &lsr)) return false; |
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return UART_GET_RECEIVER_READY(lsr);
|
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} |
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static int uart_transmitter_empty(int base_addr){ |
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uint8_t lsr; |
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if(uart_get_lsr(base_addr, &lsr)) return false; |
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return UART_GET_TRANSMITTER_EMPTY(lsr);
|
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} |
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|
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int uart_enable_int_rx(int base_addr){ |
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int ret;
|
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uint8_t ier; |
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if((ret = uart_get_ier(base_addr, &ier))) return ret; |
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ier |= UART_INT_EN_RX; |
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return uart_set_ier(base_addr, ier);
|
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} |
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int uart_disable_int_rx(int base_addr){ |
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int ret;
|
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uint8_t ier; |
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if((ret = uart_get_ier(base_addr, &ier))) return ret; |
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ier &= ~UART_INT_EN_RX; |
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return uart_set_ier(base_addr, ier);
|
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} |
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int uart_enable_int_tx(int base_addr){ |
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int ret;
|
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uint8_t ier; |
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if((ret = uart_get_ier(base_addr, &ier))) return ret; |
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ier |= UART_INT_EN_TX; |
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return uart_set_ier(base_addr, ier);
|
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} |
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int uart_disable_int_tx(int base_addr){ |
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int ret;
|
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uint8_t ier; |
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if((ret = uart_get_ier(base_addr, &ier))) return ret; |
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ier &= ~UART_INT_EN_TX; |
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return uart_set_ier(base_addr, ier);
|
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} |
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|
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/// NCTP
|
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|
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//#define NCTP_START 0x80
|
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//#define NCTP_END 0xFF
|
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#define NCTP_OK 0xFF |
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#define NCTP_NOK 0x00 |
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|
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static queue_t *out = NULL; |
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static queue_t *in = NULL; |
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static void (*process)(const uint8_t*, const size_t) = NULL; |
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|
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int nctp_init(void){ |
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out = queue_ctor(); if(out == NULL) return NULL_PTR; |
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in = queue_ctor(); if(in == NULL) return NULL_PTR; |
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return SUCCESS;
|
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} |
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int nctp_dump(void){ |
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int ret;
|
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if((ret = nctp_free())) return ret; |
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return nctp_init();
|
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} |
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int nctp_set_processor(void (*proc_func)(const uint8_t*, const size_t)){ |
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process = proc_func; |
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return SUCCESS;
|
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} |
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int nctp_free(void){ |
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while(!queue_empty(out)){
|
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free(queue_top(out)); |
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queue_pop(out); |
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} |
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while(!queue_empty(in)){
|
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free(queue_top(in)); |
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queue_pop(in); |
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} |
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return SUCCESS;
|
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} |
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|
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int nctp_send(size_t num, const uint8_t *const *ptr, const size_t *const sz){ |
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int ret;
|
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uint16_t sz_total = 0;{
|
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for(size_t i = 0; i < num; ++i) |
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sz_total += sz[i]; |
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} |
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uint8_t *tmp; |
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tmp = malloc(sizeof(uint8_t)); *tmp = *((uint8_t*)(&sz_total)+0); queue_push(out, tmp); |
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tmp = malloc(sizeof(uint8_t)); *tmp = *((uint8_t*)(&sz_total)+1); queue_push(out, tmp); |
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for(size_t i = 0; i < num; ++i){ |
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const uint8_t *p = ptr[i]; const size_t s = sz[i]; |
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for(size_t j = 0; j < s; ++j, ++p){ |
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tmp = malloc(sizeof(uint8_t)); *tmp = *p; queue_push(out, tmp);
|
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} |
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} |
331 |
|
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if(uart_transmitter_empty(COM1_ADDR)){
|
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if((ret = uart_send_char(COM1_ADDR, *(uint8_t*)queue_top(out)))) return ret; |
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queue_pop(out); |
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} |
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return SUCCESS;
|
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} |
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static int nctp_transmit(void){ |
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if(!queue_empty(out)){
|
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int ret = uart_send_char(COM1_ADDR, *(uint8_t*)queue_top(out));
|
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queue_pop(out); |
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return ret;
|
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}else return SUCCESS; |
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} |
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|
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static void nctp_process_received(){ |
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uint16_t sz = 0;{
|
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uint8_t sz0 = *(uint8_t*)queue_top(in); free(queue_top(in)); queue_pop(in); |
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uint8_t sz1 = *(uint8_t*)queue_top(in); free(queue_top(in)); queue_pop(in); |
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*((uint8_t*)(&sz)+0) = sz0;
|
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*((uint8_t*)(&sz)+1) = sz1;
|
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} |
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uint8_t *p = malloc(sz*sizeof(uint8_t));
|
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for(uint16_t i = 0; i < sz; ++i){ |
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p[i] = *(uint8_t*)queue_top(in); |
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free(queue_top(in)); queue_pop(in); |
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} |
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if(process != NULL) process(p, sz); |
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free(p); |
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} |
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|
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static int num_bytes_to_receive = 0; |
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static uint16_t szbytes_to_receive = 0; |
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static uint8_t size0 = 0; |
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static int nctp_receive(void){ |
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int ret;
|
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uint8_t c; |
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int counter_to_process = 0; |
369 |
|
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while(uart_receiver_ready(COM1_ADDR)){
|
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if((ret = uart_get_char(COM1_ADDR, &c))) return ret; |
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uint8_t *tmp = malloc(sizeof(uint8_t)); *tmp = c;
|
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|
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queue_push(in, tmp); |
375 |
|
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if (szbytes_to_receive){ // gotta receive 2nd size byte and update num_bytes |
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*((uint8_t*)(&num_bytes_to_receive)+0) = size0;
|
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*((uint8_t*)(&num_bytes_to_receive)+1) = c;
|
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szbytes_to_receive = 0;
|
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} else if(num_bytes_to_receive > 0){ |
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/* Now I know there are no more size bytes to receive.
|
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* If there are normal bytes to receive*/
|
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--num_bytes_to_receive; |
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if(num_bytes_to_receive == 0) ++counter_to_process; |
385 |
} else {
|
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/* Now I know I am not expecting anything.
|
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* The fact I received something means it is the 1st size byte */
|
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size0 = c; |
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szbytes_to_receive = 1;
|
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} |
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} |
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while(counter_to_process-- > 0) nctp_process_received(); |
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return SUCCESS;
|
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} |
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|
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static int nctp_ih_err = SUCCESS; |
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int (nctp_get_ih_error)(void){ return nctp_ih_err; } |
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void nctp_ih(void){ |
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uint8_t iir; |
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if((nctp_ih_err = uart_get_iir(COM1_ADDR, &iir))) return; |
401 |
if(UART_GET_IF_INT_PEND(iir)){
|
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switch(UART_GET_INT_PEND(iir)){
|
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case uart_int_rx: nctp_receive (); break; |
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case uart_int_tx: nctp_transmit(); break; |
405 |
case uart_int_receiver_line_stat: break; |
406 |
case uart_int_modem_stat: break; |
407 |
case uart_int_char_timeout_fifo: break; |
408 |
//default: break;
|
409 |
} |
410 |
} |
411 |
} |