root / proj / libs / uart / src / uart.c @ 313
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| 1 | 235 | up20180642 | #include <lcom/lcf.h> |
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| 2 | |||
| 3 | #include "uart.h" |
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| 4 | |||
| 5 | 275 | up20180642 | #include "queue.h" |
| 6 | 235 | up20180642 | #include "errors.h" |
| 7 | |||
| 8 | 249 | up20180642 | #define UART_BITRATE 115200 |
| 9 | #define UART_WAIT 20 //microseconds |
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| 10 | 241 | up20180642 | |
| 11 | 249 | up20180642 | #define UART_RBR 0 |
| 12 | #define UART_THR 0 |
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| 13 | #define UART_IER 1 |
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| 14 | #define UART_IIR 2 |
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| 15 | #define UART_FCR 2 |
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| 16 | #define UART_LCR 3 |
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| 17 | #define UART_MCR 4 |
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| 18 | #define UART_LSR 5 |
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| 19 | #define UART_MSR 6 |
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| 20 | #define UART_SR 7 |
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| 21 | 241 | up20180642 | |
| 22 | 249 | up20180642 | #define UART_DLL 0 |
| 23 | #define UART_DLM 1 |
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| 24 | 241 | up20180642 | |
| 25 | 249 | up20180642 | /// LCR
|
| 26 | 277 | up20180642 | #define UART_BITS_PER_CHAR_POS 0 |
| 27 | 249 | up20180642 | #define UART_STOP_BITS_POS 2 |
| 28 | #define UART_PARITY_POS 3 |
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| 29 | #define UART_BREAK_CONTROL_POS 6 |
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| 30 | #define UART_DLAB_POS 7 |
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| 31 | 241 | up20180642 | |
| 32 | 249 | up20180642 | #define UART_BITS_PER_CHAR (BIT(0) | BIT(1)) |
| 33 | #define UART_STOP_BITS (BIT(2)) |
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| 34 | #define UART_PARITY (BIT(3) | BIT(4) | BIT(5)) |
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| 35 | #define UART_BREAK_CONTROL (BIT(6)) |
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| 36 | #define UART_DLAB (BIT(7)) |
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| 37 | 241 | up20180642 | |
| 38 | 249 | up20180642 | #define UART_GET_BITS_PER_CHAR(n) (((n)&UART_BITS_PER_CHAR) + 5) |
| 39 | #define UART_GET_STOP_BITS(n) (((n)&UART_STOP_BITS)? 2 : 1) |
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| 40 | #define UART_GET_PARITY(n) (((n)&UART_PARITY )>>UART_PARITY_POS )
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| 41 | #define UART_GET_BREAK_CONTROL(n) (((n)&UART_BREAK_CONTROL)>>UART_BREAK_CONTROL_POS)
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| 42 | #define UART_GET_DLAB(n) (((n)&UART_DLAB )>>UART_DLAB_POS )
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| 43 | #define UART_GET_DIV_LATCH(m,l) ((m)<<8 | (l)) |
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| 44 | #define UART_GET_DLL(n) ((n)&0xFF) |
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| 45 | #define UART_GET_DLM(n) (((n)>>8)&0xFF) |
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| 46 | 242 | up20180642 | |
| 47 | 249 | up20180642 | /// IER
|
| 48 | 252 | up20180642 | #define UART_INT_EN_RX_POS 0 |
| 49 | #define UART_INT_EN_TX_POS 1 |
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| 50 | 249 | up20180642 | #define UART_INT_EN_RECEIVER_LINE_STAT_POS 2 |
| 51 | #define UART_INT_EN_MODEM_STAT_POS 3 |
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| 52 | 242 | up20180642 | |
| 53 | 252 | up20180642 | #define UART_INT_EN_RX (BIT(0)) |
| 54 | #define UART_INT_EN_TX (BIT(1)) |
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| 55 | 249 | up20180642 | #define UART_INT_EN_RECEIVER_LINE_STAT (BIT(2)) |
| 56 | #define UART_INT_EN_MODEM_STAT (BIT(3)) |
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| 57 | 242 | up20180642 | |
| 58 | 252 | up20180642 | #define UART_GET_INT_EN_RX(n) (((n)&UART_INT_EN_RX )>>UART_INT_EN_RX_POS )
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| 59 | #define UART_GET_INT_EN_TX(n) (((n)&UART_INT_EN_TX )>>UART_INT_EN_TX_POS )
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| 60 | #define UART_GET_INT_EN_RECEIVER_LINE_STAT(n) (((n)&UART_INT_EN_RECEIVER_LINE_STAT)>>UART_INT_EN_RECEIVER_LINE_STAT_POS)
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| 61 | #define UART_GET_INT_EN_MODEM_STAT(n) (((n)&UART_INT_EN_MODEM_STAT )>>UART_INT_EN_MODEM_STAT_POS )
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| 62 | 249 | up20180642 | |
| 63 | /// LSR
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| 64 | #define UART_RECEIVER_READY_POS 0 |
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| 65 | 261 | up20180642 | #define UART_OVERRUN_ERROR_POS 1 |
| 66 | #define UART_PARITY_ERROR_POS 2 |
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| 67 | #define UART_FRAMING_ERROR_POS 3 |
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| 68 | 249 | up20180642 | #define UART_TRANSMITTER_EMPTY_POS 5 |
| 69 | |||
| 70 | #define UART_RECEIVER_READY (BIT(0)) |
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| 71 | 261 | up20180642 | #define UART_OVERRUN_ERROR (BIT(1)) |
| 72 | #define UART_PARITY_ERROR (BIT(2)) |
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| 73 | #define UART_FRAMING_ERROR (BIT(3)) |
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| 74 | 249 | up20180642 | #define UART_TRANSMITTER_EMPTY (BIT(5)) |
| 75 | |||
| 76 | #define UART_GET_RECEIVER_READY(n) (((n)&UART_RECEIVER_READY )>>UART_RECEIVER_READY_POS )
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| 77 | 261 | up20180642 | #define UART_GET_OVERRUN_ERROR (((n)&UART_OVERRUN_ERROR )>>UART_OVERRUN_ERROR_POS )
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| 78 | #define UART_GET_PARITY_ERROR (((n)&UART_PARITY_ERROR )>>UART_PARITY_ERROR_POS )
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| 79 | #define UART_GET_FRAMING_ERROR (((n)&UART_FRAMING_ERROR )>>UART_FRAMING_ERROR_POS )
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| 80 | 249 | up20180642 | #define UART_GET_TRANSMITTER_EMPTY(n) (((n)&UART_TRANSMITTER_EMPTY )>>UART_TRANSMITTER_EMPTY_POS )
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| 81 | |||
| 82 | 275 | up20180642 | /// IIR
|
| 83 | 277 | up20180642 | #define UART_INT_PEND_POS 1 |
| 84 | |||
| 85 | #define UART_INT_PEND (BIT(3)|BIT(2)|BIT(1)) |
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| 86 | |||
| 87 | 275 | up20180642 | #define UART_GET_IF_INT_PEND(n) (!((n)&1)) |
| 88 | 277 | up20180642 | typedef enum { |
| 89 | uart_int_receiver_line_stat = ( BIT(1) | BIT(0)), |
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| 90 | uart_int_rx = ( BIT(1) ),
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| 91 | uart_int_char_timeout_fifo = (BIT(2) | BIT(1) ), |
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| 92 | uart_int_tx = ( BIT(0)),
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| 93 | uart_int_modem_stat = (0)
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| 94 | } uart_int_code; |
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| 95 | #define UART_GET_INT_PEND(n) ((uart_int_code)(((n)&UART_INT_PEND)>>UART_INT_PEND_POS))
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| 96 | 275 | up20180642 | |
| 97 | 263 | up20180642 | int (subscribe_uart_interrupt)(uint8_t interrupt_bit, int *interrupt_id) { |
| 98 | if (interrupt_id == NULL) return 1; |
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| 99 | *interrupt_id = interrupt_bit; |
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| 100 | return (sys_irqsetpolicy(COM1_IRQ, IRQ_REENABLE | IRQ_EXCLUSIVE, interrupt_id));
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| 101 | } |
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| 102 | |||
| 103 | 252 | up20180642 | static void uart_parse_config(uart_config *config){ |
| 104 | /// LCR
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| 105 | config->bits_per_char = UART_GET_BITS_PER_CHAR (config->lcr); |
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| 106 | config->stop_bits = UART_GET_STOP_BITS (config->lcr); |
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| 107 | config->parity = UART_GET_PARITY (config->lcr); if((config->parity & BIT(0)) == 0) config->parity = uart_parity_none; |
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| 108 | config->break_control = UART_GET_BREAK_CONTROL (config->lcr); |
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| 109 | config->dlab = UART_GET_DLAB (config->lcr); |
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| 110 | /// IER
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| 111 | config->received_data_int = UART_GET_INT_EN_RX (config->ier); |
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| 112 | config->transmitter_empty_int = UART_GET_INT_EN_TX (config->ier); |
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| 113 | config->receiver_line_stat_int = UART_GET_INT_EN_RECEIVER_LINE_STAT(config->ier); |
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| 114 | config->modem_stat_int = UART_GET_INT_EN_MODEM_STAT (config->ier); |
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| 115 | /// DIV LATCH
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| 116 | config->divisor_latch = UART_GET_DIV_LATCH(config->dlm, config->dll); |
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| 117 | } |
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| 118 | |||
| 119 | static int uart_get_lcr(int base_addr, uint8_t *p){ |
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| 120 | return util_sys_inb(base_addr+UART_LCR, p);
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| 121 | } |
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| 122 | static int uart_set_lcr(int base_addr, uint8_t config){ |
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| 123 | if(sys_outb(base_addr+UART_LCR, config)) return WRITE_ERROR; |
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| 124 | return SUCCESS;
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| 125 | } |
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| 126 | static int uart_get_lsr(int base_addr, uint8_t *p){ |
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| 127 | return util_sys_inb(base_addr+UART_LSR, p);
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| 128 | } |
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| 129 | 275 | up20180642 | static int uart_get_iir(int base_addr, uint8_t *p){ |
| 130 | return util_sys_inb(base_addr+UART_IIR, p);
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| 131 | } |
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| 132 | 252 | up20180642 | |
| 133 | static int uart_enable_divisor_latch(int base_addr){ |
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| 134 | int ret = SUCCESS;
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| 135 | uint8_t conf; if((ret = uart_get_lcr(base_addr, &conf))) return ret; |
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| 136 | return uart_set_lcr(base_addr, conf | UART_DLAB);
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| 137 | } |
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| 138 | static int uart_disable_divisor_latch(int base_addr){ |
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| 139 | int ret = SUCCESS;
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| 140 | uint8_t conf; if((ret = uart_get_lcr(base_addr, &conf))) return ret; |
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| 141 | return uart_set_lcr(base_addr, conf & (~UART_DLAB));
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| 142 | } |
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| 143 | |||
| 144 | static int uart_get_ier(int base_addr, uint8_t *p){ |
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| 145 | int ret;
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| 146 | if((ret = uart_disable_divisor_latch(base_addr))) return ret; |
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| 147 | return util_sys_inb(base_addr+UART_IER, p);
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| 148 | } |
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| 149 | static int uart_set_ier(int base_addr, uint8_t n){ |
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| 150 | int ret;
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| 151 | if((ret = uart_disable_divisor_latch(base_addr))) return ret; |
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| 152 | if(sys_outb(base_addr+UART_IER, n)) return WRITE_ERROR; |
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| 153 | return SUCCESS;
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| 154 | } |
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| 155 | |||
| 156 | 235 | up20180642 | int uart_get_config(int base_addr, uart_config *config){ |
| 157 | int ret = SUCCESS;
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| 158 | |||
| 159 | config->base_addr = base_addr; |
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| 160 | |||
| 161 | 252 | up20180642 | if((ret = uart_get_lcr(base_addr, &config->lcr))) return ret; |
| 162 | 235 | up20180642 | |
| 163 | 252 | up20180642 | if((ret = uart_get_ier(base_addr, &config->ier))) return ret; |
| 164 | 242 | up20180642 | |
| 165 | if((ret = uart_enable_divisor_latch (base_addr))) return ret; |
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| 166 | 235 | up20180642 | if((ret = util_sys_inb(base_addr+UART_DLL, &config->dll ))) return ret; |
| 167 | if((ret = util_sys_inb(base_addr+UART_DLM, &config->dlm ))) return ret; |
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| 168 | 242 | up20180642 | if((ret = uart_disable_divisor_latch(base_addr))) return ret; |
| 169 | 235 | up20180642 | |
| 170 | uart_parse_config(config); |
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| 171 | return ret;
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| 172 | } |
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| 173 | void uart_print_config(uart_config config){
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| 174 | 249 | up20180642 | |
| 175 | printf("%s configuration:\n", (config.base_addr == COM1_ADDR ? "COM1" : "COM2")); |
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| 176 | printf("\tLCR = 0x%X: %d bits per char\t %d stop bits\t", config.lcr, config.bits_per_char, config.stop_bits);
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| 177 | if((config.parity&BIT(0)) == 0) printf("NO parity\n"); |
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| 178 | 235 | up20180642 | else switch(config.parity){ |
| 179 | 249 | up20180642 | case uart_parity_odd : printf("ODD parity\n" ); break; |
| 180 | case uart_parity_even: printf("EVEN parity\n" ); break; |
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| 181 | 235 | up20180642 | case uart_parity_par1: printf("parity bit is 1\n"); break; |
| 182 | case uart_parity_par0: printf("parity bit is 0\n"); break; |
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| 183 | default : printf("invalid\n" ); break; |
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| 184 | } |
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| 185 | 249 | up20180642 | printf("\tDLM = 0x%02X DLL=0x%02X: bitrate = %d bps\n", config.dlm, config.dll, UART_BITRATE/config.divisor_latch);
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| 186 | printf("\tIER = 0x%02X: Rx interrupts: %s\tTx interrupts: %s\n", config.ier,
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| 187 | (config.received_data_int ? "ENABLED":"DISABLED"), |
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| 188 | (config.transmitter_empty_int ? "ENABLED":"DISABLED")); |
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| 189 | 235 | up20180642 | } |
| 190 | |||
| 191 | int uart_set_bits_per_character(int base_addr, uint8_t bits_per_char){ |
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| 192 | if(bits_per_char < 5 || bits_per_char > 8) return INVALID_ARG; |
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| 193 | int ret = SUCCESS;
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| 194 | bits_per_char = (bits_per_char-5)&0x3; |
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| 195 | 252 | up20180642 | uint8_t conf; if((ret = uart_get_lcr(base_addr, &conf))) return ret; |
| 196 | 235 | up20180642 | conf = (conf & (~UART_BITS_PER_CHAR)) | bits_per_char; |
| 197 | 252 | up20180642 | return uart_set_lcr(base_addr, conf);
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| 198 | 235 | up20180642 | } |
| 199 | int uart_set_stop_bits(int base_addr, uint8_t stop){ |
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| 200 | if(stop != 1 && stop != 2) return INVALID_ARG; |
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| 201 | int ret = SUCCESS;
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| 202 | stop -= 1;
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| 203 | stop = (stop&1)<<2; |
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| 204 | 252 | up20180642 | uint8_t conf; if((ret = uart_get_lcr(base_addr, &conf))) return ret; |
| 205 | 235 | up20180642 | conf = (conf & (~UART_STOP_BITS)) | stop; |
| 206 | 252 | up20180642 | return uart_set_lcr(base_addr, conf);
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| 207 | 235 | up20180642 | } |
| 208 | int uart_set_parity(int base_addr, uart_parity par){ |
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| 209 | int ret = SUCCESS;
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| 210 | uint8_t parity = par << 3;
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| 211 | 252 | up20180642 | uint8_t conf; if((ret = uart_get_lcr(base_addr, &conf))) return ret; |
| 212 | 235 | up20180642 | conf = (conf & (~UART_PARITY)) | parity; |
| 213 | 252 | up20180642 | return uart_set_lcr(base_addr, conf);
|
| 214 | 235 | up20180642 | } |
| 215 | 241 | up20180642 | int uart_set_bit_rate(int base_addr, float bit_rate){ |
| 216 | 235 | up20180642 | int ret = SUCCESS;
|
| 217 | uint16_t latch = UART_BITRATE/bit_rate; |
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| 218 | 241 | up20180642 | uint8_t dll = UART_GET_DLL(latch); |
| 219 | uint8_t dlm = UART_GET_DLM(latch); |
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| 220 | 235 | up20180642 | if((ret = uart_enable_divisor_latch(base_addr))) return ret; |
| 221 | if(sys_outb(base_addr+UART_DLL, dll)) return WRITE_ERROR; |
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| 222 | if(sys_outb(base_addr+UART_DLM, dlm)) return WRITE_ERROR; |
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| 223 | 249 | up20180642 | if((ret = uart_disable_divisor_latch(base_addr))) return ret; |
| 224 | 235 | up20180642 | return SUCCESS;
|
| 225 | } |
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| 226 | 249 | up20180642 | |
| 227 | 252 | up20180642 | static int uart_get_char(int base_addr, uint8_t *p){ |
| 228 | 249 | up20180642 | int ret;
|
| 229 | if((ret = uart_disable_divisor_latch(base_addr))) return ret; |
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| 230 | return util_sys_inb(base_addr+UART_RBR, p);
|
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| 231 | } |
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| 232 | 252 | up20180642 | static int uart_send_char(int base_addr, uint8_t c){ |
| 233 | 249 | up20180642 | int ret;
|
| 234 | if((ret = uart_disable_divisor_latch(base_addr))) return ret; |
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| 235 | 252 | up20180642 | if(sys_outb(base_addr+UART_THR, c)) return WRITE_ERROR; |
| 236 | 249 | up20180642 | return SUCCESS;
|
| 237 | } |
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| 238 | 252 | up20180642 | static int uart_receiver_ready(int base_addr){ |
| 239 | 249 | up20180642 | uint8_t lsr; |
| 240 | if(uart_get_lsr(base_addr, &lsr)) return false; |
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| 241 | return UART_GET_RECEIVER_READY(lsr);
|
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| 242 | } |
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| 243 | 252 | up20180642 | static int uart_transmitter_empty(int base_addr){ |
| 244 | 249 | up20180642 | uint8_t lsr; |
| 245 | if(uart_get_lsr(base_addr, &lsr)) return false; |
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| 246 | return UART_GET_TRANSMITTER_EMPTY(lsr);
|
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| 247 | } |
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| 248 | 252 | up20180642 | |
| 249 | int uart_enable_int_rx(int base_addr){ |
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| 250 | int ret;
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| 251 | uint8_t ier; |
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| 252 | if((ret = uart_get_ier(base_addr, &ier))) return ret; |
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| 253 | ier |= UART_INT_EN_RX; |
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| 254 | return uart_set_ier(base_addr, ier);
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| 255 | } |
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| 256 | int uart_disable_int_rx(int base_addr){ |
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| 257 | int ret;
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| 258 | uint8_t ier; |
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| 259 | if((ret = uart_get_ier(base_addr, &ier))) return ret; |
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| 260 | ier &= ~UART_INT_EN_RX; |
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| 261 | return uart_set_ier(base_addr, ier);
|
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| 262 | } |
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| 263 | int uart_enable_int_tx(int base_addr){ |
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| 264 | int ret;
|
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| 265 | uint8_t ier; |
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| 266 | if((ret = uart_get_ier(base_addr, &ier))) return ret; |
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| 267 | ier |= UART_INT_EN_TX; |
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| 268 | return uart_set_ier(base_addr, ier);
|
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| 269 | } |
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| 270 | int uart_disable_int_tx(int base_addr){ |
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| 271 | int ret;
|
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| 272 | uint8_t ier; |
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| 273 | if((ret = uart_get_ier(base_addr, &ier))) return ret; |
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| 274 | ier &= ~UART_INT_EN_TX; |
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| 275 | return uart_set_ier(base_addr, ier);
|
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| 276 | } |
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| 277 | |||
| 278 | 283 | up20180642 | /// NCTP
|
| 279 | 261 | up20180642 | |
| 280 | #define NCTP_START 0x80 |
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| 281 | #define NCTP_END 0xFF |
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| 282 | #define NCTP_OK 0xFF |
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| 283 | #define NCTP_NOK 0x00 |
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| 284 | |||
| 285 | 275 | up20180642 | queue_t *out = NULL;
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| 286 | queue_t *in = NULL;
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| 287 | 298 | up20180642 | void (*process)(const uint8_t*, const size_t) = NULL; |
| 288 | 261 | up20180642 | |
| 289 | 298 | up20180642 | int nctp_init(void){ |
| 290 | 275 | up20180642 | out = queue_ctor(); if(out == NULL) return NULL_PTR; |
| 291 | in = queue_ctor(); if(in == NULL) return NULL_PTR; |
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| 292 | 297 | up20180642 | return SUCCESS;
|
| 293 | } |
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| 294 | 298 | up20180642 | int nctp_dump(void){ |
| 295 | int ret;
|
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| 296 | if((ret = nctp_free())) return ret; |
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| 297 | return nctp_init();
|
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| 298 | } |
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| 299 | 297 | up20180642 | int nctp_set_processor(void (*proc_func)(const uint8_t*, const size_t)){ |
| 300 | 287 | up20180642 | process = proc_func; |
| 301 | 275 | up20180642 | return SUCCESS;
|
| 302 | 261 | up20180642 | } |
| 303 | 275 | up20180642 | int nctp_free(void){ |
| 304 | while(!queue_empty(out)){
|
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| 305 | free(queue_top(out)); |
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| 306 | queue_pop(out); |
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| 307 | 261 | up20180642 | } |
| 308 | 275 | up20180642 | while(!queue_empty(in)){
|
| 309 | free(queue_top(in)); |
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| 310 | queue_pop(in); |
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| 311 | 261 | up20180642 | } |
| 312 | 275 | up20180642 | return SUCCESS;
|
| 313 | 261 | up20180642 | } |
| 314 | |||
| 315 | 275 | up20180642 | int nctp_send(size_t num, uint8_t* ptr[], size_t sz[]){
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| 316 | 261 | up20180642 | {
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| 317 | 277 | up20180642 | size_t cnt = 0;
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| 318 | 261 | up20180642 | for(size_t i = 0; i < num; ++i){ |
| 319 | cnt += sz[i]; |
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| 320 | 277 | up20180642 | if(cnt > queue_max_size) return TRANS_REFUSED; |
| 321 | 261 | up20180642 | } |
| 322 | } |
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| 323 | int ret;
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| 324 | 275 | up20180642 | uint8_t *tmp; |
| 325 | tmp = malloc(sizeof(uint8_t)); *tmp = NCTP_START; queue_push(out, tmp);
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| 326 | 261 | up20180642 | for(size_t i = 0; i < num; ++i){ |
| 327 | uint8_t *p = ptr[i]; size_t s = sz[i]; |
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| 328 | 275 | up20180642 | for(size_t j = 0; j < s; ++j, ++p){ |
| 329 | tmp = malloc(sizeof(uint8_t)); *tmp = *p; queue_push(out, tmp);
|
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| 330 | } |
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| 331 | 261 | up20180642 | } |
| 332 | 275 | up20180642 | tmp = malloc(sizeof(uint8_t)); *tmp = NCTP_END; queue_push(out, tmp);
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| 333 | if(uart_transmitter_empty(COM1_ADDR)){
|
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| 334 | if((ret = uart_send_char(COM1_ADDR, *(uint8_t*)queue_top(out)))) return ret; |
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| 335 | queue_pop(out); |
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| 336 | } |
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| 337 | 249 | up20180642 | return SUCCESS;
|
| 338 | } |
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| 339 | 275 | up20180642 | static int nctp_transmit(void){ |
| 340 | if(!queue_empty(out)){
|
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| 341 | int ret = uart_send_char(COM1_ADDR, *(uint8_t*)queue_top(out));
|
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| 342 | queue_pop(out); |
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| 343 | return ret;
|
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| 344 | }else return SUCCESS; |
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| 345 | 269 | up20180642 | } |
| 346 | 278 | up20180642 | |
| 347 | 287 | up20180642 | static void nctp_process_received(){ |
| 348 | 275 | up20180642 | free(queue_top(in)); queue_pop(in); |
| 349 | 287 | up20180642 | size_t sz = 1024; uint8_t *p = malloc(sz*sizeof(uint8_t)); |
| 350 | size_t i = 0;
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| 351 | 275 | up20180642 | while(*(uint8_t*)queue_top(in) != NCTP_END){
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| 352 | 287 | up20180642 | //printf("%c\n", *(uint8_t*)queue_top(in));
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| 353 | p[i++] = *(uint8_t*)queue_top(in); |
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| 354 | 275 | up20180642 | free(queue_top(in)); queue_pop(in); |
| 355 | 287 | up20180642 | if(i >= sz) p = realloc(p, sz=2*sz); |
| 356 | 275 | up20180642 | } |
| 357 | free(queue_top(in)); queue_pop(in); |
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| 358 | 298 | up20180642 | if(process != NULL) process(p, i); |
| 359 | 287 | up20180642 | free(p); |
| 360 | 275 | up20180642 | } |
| 361 | static int nctp_receive(void){ |
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| 362 | 249 | up20180642 | int ret;
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| 363 | 261 | up20180642 | uint8_t c; |
| 364 | 277 | up20180642 | int num_ends = 0; |
| 365 | 275 | up20180642 | while(uart_receiver_ready(COM1_ADDR)){
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| 366 | if((ret = uart_get_char(COM1_ADDR, &c))) return ret; |
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| 367 | uint8_t *tmp = malloc(sizeof(uint8_t)); *tmp = c;
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| 368 | queue_push(in, tmp); |
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| 369 | 277 | up20180642 | if(c == NCTP_END) ++num_ends;
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| 370 | 261 | up20180642 | } |
| 371 | 287 | up20180642 | while(num_ends-- > 0) nctp_process_received(); |
| 372 | 275 | up20180642 | return SUCCESS;
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| 373 | 249 | up20180642 | } |
| 374 | 275 | up20180642 | |
| 375 | int nctp_ih_err = SUCCESS;
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| 376 | void nctp_ih(void){ |
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| 377 | uint8_t iir; |
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| 378 | if((nctp_ih_err = uart_get_iir(COM1_ADDR, &iir))) return; |
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| 379 | if(UART_GET_IF_INT_PEND(iir)){
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| 380 | switch(UART_GET_INT_PEND(iir)){
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| 381 | 277 | up20180642 | case uart_int_rx: nctp_receive (); break; |
| 382 | case uart_int_tx: nctp_transmit(); break; |
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| 383 | 275 | up20180642 | default: break; |
| 384 | } |
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| 385 | } |
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| 386 | 269 | up20180642 | } |