root / lab2 / timer.c @ 30
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1 | 4 | up20180655 | #include <lcom/lcf.h> |
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2 | #include <lcom/timer.h> |
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3 | |||
4 | #include <stdint.h> |
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5 | |||
6 | #include "i8254.h" |
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7 | |||
8 | int (timer_set_frequency)(uint8_t timer, uint32_t freq) {
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9 | 18 | up20180655 | |
10 | // Frequencies out this range are not supported (by limitation of hardware)
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11 | 27 | up20180655 | if (freq > TIMER_FREQ || freq < TIMER_MIN_FREQ) {
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12 | printf("%s: Frequency out of range, must be between %d and %d.\n", __func__, TIMER_MIN_FREQ, TIMER_FREQ);
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13 | return 1; |
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14 | } |
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15 | 18 | up20180655 | |
16 | 10 | up20180655 | uint8_t status = 0;
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17 | if (timer_get_conf(timer, &status)) return 1; |
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18 | //Make command
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19 | uint8_t write_cmd = 0;
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20 | //Select timer
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21 | switch(timer) {
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22 | 11 | up20180655 | case 0: write_cmd |= TIMER_SEL0; break; |
23 | case 1: write_cmd |= TIMER_SEL1; break; |
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24 | case 2: write_cmd |= TIMER_SEL2; break; |
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25 | 29 | up20180655 | default: return 1; |
26 | 10 | up20180655 | } |
27 | //Change both LSB and MSB
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28 | write_cmd |= TIMER_LSB_MSB; |
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29 | //Keep 4 least significant bits
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30 | write_cmd |= (status & (TIMER_MODE_MASK | TIMER_BCD)); |
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31 | //Write cmd
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32 | 11 | up20180655 | if (sys_outb(TIMER_CTRL, write_cmd)) return 1; |
33 | 10 | up20180655 | |
34 | 11 | up20180655 | // counter_init = clock/freq
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35 | 15 | up20180655 | uint16_t counter_init = (uint16_t)(TIMER_FREQ / freq); |
36 | 10 | up20180655 | |
37 | 11 | up20180655 | int timer_port = 0; |
38 | switch(timer) {
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39 | 12 | up20180655 | case 0: timer_port = TIMER_0; break; |
40 | case 1: timer_port = TIMER_1; break; |
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41 | case 2: timer_port = TIMER_2; break; |
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42 | 29 | up20180655 | default: return 1; |
43 | 11 | up20180655 | } |
44 | 15 | up20180655 | uint8_t lsb = 0, msb = 0; |
45 | 29 | up20180655 | /* Split the 16 bits word in two bytes */
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46 | 15 | up20180655 | if (util_get_LSB(counter_init, &lsb)) return 1; |
47 | if (util_get_MSB(counter_init, &msb)) return 1; |
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48 | 11 | up20180655 | |
49 | 29 | up20180655 | /* Write the 8 LSB of the counter */
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50 | 15 | up20180655 | if (sys_outb(timer_port, lsb)) return 1; |
51 | 29 | up20180655 | /* Write the 8 MSB of the counter */
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52 | 15 | up20180655 | if (sys_outb(timer_port, msb)) return 1; |
53 | 11 | up20180655 | |
54 | 15 | up20180655 | return 0; |
55 | 4 | up20180655 | } |
56 | |||
57 | 27 | up20180655 | int hook_id;
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58 | 22 | up20180642 | |
59 | 4 | up20180655 | int (timer_subscribe_int)(uint8_t *bit_no) {
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60 | 29 | up20180655 | if(bit_no == NULL) return 1; |
61 | 27 | up20180655 | hook_id = 2;
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62 | 25 | up20180655 | *bit_no = hook_id; |
63 | 29 | up20180655 | /* Subscribe Timer 0 Interrupts */
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64 | 27 | up20180655 | return sys_irqsetpolicy(TIMER0_IRQ, IRQ_REENABLE, &hook_id);
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65 | 4 | up20180655 | } |
66 | |||
67 | 22 | up20180642 | int (timer_unsubscribe_int)() {
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68 | 29 | up20180655 | /* Unsubscribe Timer 0 Interrupts */
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69 | 19 | up20180642 | if(sys_irqrmpolicy(&hook_id)) return 1; |
70 | return 0; |
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71 | 4 | up20180655 | } |
72 | |||
73 | 26 | up20180642 | int no_interrupts = 0; |
74 | 4 | up20180655 | void (timer_int_handler)() {
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75 | 20 | up20180655 | no_interrupts++; |
76 | 4 | up20180655 | } |
77 | |||
78 | int (timer_get_conf)(uint8_t timer, uint8_t *st) {
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79 | 26 | up20180642 | if(st == NULL) return 1; |
80 | 9 | up20180642 | // Write read-back command to TIMER_CTRL
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81 | 5 | up20180642 | u32_t cmd = TIMER_RB_CMD | TIMER_RB_COUNT_ | TIMER_RB_SEL(timer); |
82 | 10 | up20180655 | if(sys_outb(TIMER_CTRL, cmd)) return 1; |
83 | 5 | up20180642 | int read_port;
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84 | 7 | up20180655 | switch(timer) {
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85 | 5 | up20180642 | case 0: read_port = TIMER_0; break; |
86 | case 1: read_port = TIMER_1; break; |
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87 | case 2: read_port = TIMER_2; break; |
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88 | 29 | up20180655 | default: return 1; |
89 | 5 | up20180642 | } |
90 | if(util_sys_inb(read_port, st)) return 1; |
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91 | return 0; |
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92 | 4 | up20180655 | } |
93 | |||
94 | 6 | up20180642 | int (timer_display_conf)(uint8_t timer, uint8_t st, enum timer_status_field field) { |
95 | union timer_status_field_val conf;
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96 | uint8_t in_mode; |
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97 | 16 | up20180642 | switch(field){
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98 | case tsf_all:
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99 | 29 | up20180655 | conf.byte = st; /* Full Status Byte */
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100 | 16 | up20180642 | break;
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101 | case tsf_initial:
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102 | 29 | up20180655 | /* Counter Initial Value Loading Mode */
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103 | 16 | up20180642 | in_mode = (st & TIMER_INMODE_MASK) >> TIMER_INMODE_POS; |
104 | switch(in_mode){
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105 | case 0: conf.in_mode = INVAL_val ; break; //000 |
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106 | case 1: conf.in_mode = LSB_only ; break; //001 |
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107 | case 2: conf.in_mode = MSB_only ; break; //010 |
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108 | case 3: conf.in_mode = MSB_after_LSB; break; //011 |
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109 | 29 | up20180655 | default: return 1; |
110 | 16 | up20180642 | } |
111 | break;
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112 | case tsf_mode:
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113 | 29 | up20180655 | /* Counting Mode */
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114 | 16 | up20180642 | conf.count_mode = (st & TIMER_MODE_MASK)>>TIMER_MODE_POS; |
115 | 17 | up20180642 | if(conf.count_mode == TIMER_MODE_2ALT || conf.count_mode == TIMER_MODE_3ALT)
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116 | 16 | up20180642 | conf.count_mode &= TIMER_MODE_RED2; |
117 | break;
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118 | case tsf_base:
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119 | 29 | up20180655 | /* Representation of Counter Initial Value */
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120 | 16 | up20180642 | conf.bcd = st & TIMER_BCD; |
121 | break;
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122 | 29 | up20180655 | default: return 1; |
123 | 5 | up20180642 | } |
124 | 16 | up20180642 | if(timer_print_config(timer, field, conf)) return 1; |
125 | 6 | up20180642 | return 0; |
126 | } |