root / proj / src / uart.c @ 275
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1 | 235 | up20180642 | #include <lcom/lcf.h> |
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2 | |||
3 | #include "uart.h" |
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4 | |||
5 | 275 | up20180642 | #include "queue.h" |
6 | 235 | up20180642 | #include "errors.h" |
7 | |||
8 | 249 | up20180642 | #define UART_BITRATE 115200 |
9 | #define UART_WAIT 20 //microseconds |
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10 | 241 | up20180642 | |
11 | 249 | up20180642 | #define UART_RBR 0 |
12 | #define UART_THR 0 |
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13 | #define UART_IER 1 |
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14 | #define UART_IIR 2 |
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15 | #define UART_FCR 2 |
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16 | #define UART_LCR 3 |
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17 | #define UART_MCR 4 |
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18 | #define UART_LSR 5 |
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19 | #define UART_MSR 6 |
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20 | #define UART_SR 7 |
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21 | 241 | up20180642 | |
22 | 249 | up20180642 | #define UART_DLL 0 |
23 | #define UART_DLM 1 |
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24 | 241 | up20180642 | |
25 | 249 | up20180642 | /// LCR
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26 | #define UART_BITS_PER_CHAR_POS 0 |
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27 | #define UART_STOP_BITS_POS 2 |
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28 | #define UART_PARITY_POS 3 |
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29 | #define UART_BREAK_CONTROL_POS 6 |
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30 | #define UART_DLAB_POS 7 |
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31 | 241 | up20180642 | |
32 | 249 | up20180642 | #define UART_BITS_PER_CHAR (BIT(0) | BIT(1)) |
33 | #define UART_STOP_BITS (BIT(2)) |
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34 | #define UART_PARITY (BIT(3) | BIT(4) | BIT(5)) |
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35 | #define UART_BREAK_CONTROL (BIT(6)) |
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36 | #define UART_DLAB (BIT(7)) |
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37 | 241 | up20180642 | |
38 | 249 | up20180642 | #define UART_GET_BITS_PER_CHAR(n) (((n)&UART_BITS_PER_CHAR) + 5) |
39 | #define UART_GET_STOP_BITS(n) (((n)&UART_STOP_BITS)? 2 : 1) |
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40 | #define UART_GET_PARITY(n) (((n)&UART_PARITY )>>UART_PARITY_POS )
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41 | #define UART_GET_BREAK_CONTROL(n) (((n)&UART_BREAK_CONTROL)>>UART_BREAK_CONTROL_POS)
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42 | #define UART_GET_DLAB(n) (((n)&UART_DLAB )>>UART_DLAB_POS )
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43 | #define UART_GET_DIV_LATCH(m,l) ((m)<<8 | (l)) |
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44 | #define UART_GET_DLL(n) ((n)&0xFF) |
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45 | #define UART_GET_DLM(n) (((n)>>8)&0xFF) |
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46 | 242 | up20180642 | |
47 | 249 | up20180642 | /// IER
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48 | 252 | up20180642 | #define UART_INT_EN_RX_POS 0 |
49 | #define UART_INT_EN_TX_POS 1 |
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50 | 249 | up20180642 | #define UART_INT_EN_RECEIVER_LINE_STAT_POS 2 |
51 | #define UART_INT_EN_MODEM_STAT_POS 3 |
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52 | 242 | up20180642 | |
53 | 252 | up20180642 | #define UART_INT_EN_RX (BIT(0)) |
54 | #define UART_INT_EN_TX (BIT(1)) |
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55 | 249 | up20180642 | #define UART_INT_EN_RECEIVER_LINE_STAT (BIT(2)) |
56 | #define UART_INT_EN_MODEM_STAT (BIT(3)) |
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57 | 242 | up20180642 | |
58 | 252 | up20180642 | #define UART_GET_INT_EN_RX(n) (((n)&UART_INT_EN_RX )>>UART_INT_EN_RX_POS )
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59 | #define UART_GET_INT_EN_TX(n) (((n)&UART_INT_EN_TX )>>UART_INT_EN_TX_POS )
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60 | #define UART_GET_INT_EN_RECEIVER_LINE_STAT(n) (((n)&UART_INT_EN_RECEIVER_LINE_STAT)>>UART_INT_EN_RECEIVER_LINE_STAT_POS)
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61 | #define UART_GET_INT_EN_MODEM_STAT(n) (((n)&UART_INT_EN_MODEM_STAT )>>UART_INT_EN_MODEM_STAT_POS )
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62 | 249 | up20180642 | |
63 | /// LSR
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64 | #define UART_RECEIVER_READY_POS 0 |
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65 | 261 | up20180642 | #define UART_OVERRUN_ERROR_POS 1 |
66 | #define UART_PARITY_ERROR_POS 2 |
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67 | #define UART_FRAMING_ERROR_POS 3 |
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68 | 249 | up20180642 | #define UART_TRANSMITTER_EMPTY_POS 5 |
69 | |||
70 | #define UART_RECEIVER_READY (BIT(0)) |
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71 | 261 | up20180642 | #define UART_OVERRUN_ERROR (BIT(1)) |
72 | #define UART_PARITY_ERROR (BIT(2)) |
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73 | #define UART_FRAMING_ERROR (BIT(3)) |
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74 | 249 | up20180642 | #define UART_TRANSMITTER_EMPTY (BIT(5)) |
75 | |||
76 | #define UART_GET_RECEIVER_READY(n) (((n)&UART_RECEIVER_READY )>>UART_RECEIVER_READY_POS )
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77 | 261 | up20180642 | #define UART_GET_OVERRUN_ERROR (((n)&UART_OVERRUN_ERROR )>>UART_OVERRUN_ERROR_POS )
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78 | #define UART_GET_PARITY_ERROR (((n)&UART_PARITY_ERROR )>>UART_PARITY_ERROR_POS )
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79 | #define UART_GET_FRAMING_ERROR (((n)&UART_FRAMING_ERROR )>>UART_FRAMING_ERROR_POS )
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80 | 249 | up20180642 | #define UART_GET_TRANSMITTER_EMPTY(n) (((n)&UART_TRANSMITTER_EMPTY )>>UART_TRANSMITTER_EMPTY_POS )
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81 | |||
82 | 275 | up20180642 | /// IIR
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83 | #define UART_GET_IF_INT_PEND(n) (!((n)&1)) |
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84 | #define UART_GET_INT_PEND(n) (((n)&0xE)>>1) |
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85 | #define UART_INT_RX 0x2 //0b010 |
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86 | #define UART_INT_TX 0x1 //0b001 |
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87 | |||
88 | 263 | up20180642 | int (subscribe_uart_interrupt)(uint8_t interrupt_bit, int *interrupt_id) { |
89 | if (interrupt_id == NULL) return 1; |
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90 | *interrupt_id = interrupt_bit; |
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91 | return (sys_irqsetpolicy(COM1_IRQ, IRQ_REENABLE | IRQ_EXCLUSIVE, interrupt_id));
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92 | } |
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93 | |||
94 | 252 | up20180642 | static void uart_parse_config(uart_config *config){ |
95 | /// LCR
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96 | config->bits_per_char = UART_GET_BITS_PER_CHAR (config->lcr); |
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97 | config->stop_bits = UART_GET_STOP_BITS (config->lcr); |
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98 | config->parity = UART_GET_PARITY (config->lcr); if((config->parity & BIT(0)) == 0) config->parity = uart_parity_none; |
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99 | config->break_control = UART_GET_BREAK_CONTROL (config->lcr); |
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100 | config->dlab = UART_GET_DLAB (config->lcr); |
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101 | /// IER
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102 | config->received_data_int = UART_GET_INT_EN_RX (config->ier); |
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103 | config->transmitter_empty_int = UART_GET_INT_EN_TX (config->ier); |
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104 | config->receiver_line_stat_int = UART_GET_INT_EN_RECEIVER_LINE_STAT(config->ier); |
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105 | config->modem_stat_int = UART_GET_INT_EN_MODEM_STAT (config->ier); |
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106 | /// DIV LATCH
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107 | config->divisor_latch = UART_GET_DIV_LATCH(config->dlm, config->dll); |
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108 | } |
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109 | |||
110 | static int uart_get_lcr(int base_addr, uint8_t *p){ |
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111 | return util_sys_inb(base_addr+UART_LCR, p);
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112 | } |
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113 | static int uart_set_lcr(int base_addr, uint8_t config){ |
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114 | if(sys_outb(base_addr+UART_LCR, config)) return WRITE_ERROR; |
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115 | return SUCCESS;
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116 | } |
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117 | static int uart_get_lsr(int base_addr, uint8_t *p){ |
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118 | return util_sys_inb(base_addr+UART_LSR, p);
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119 | } |
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120 | 275 | up20180642 | static int uart_get_iir(int base_addr, uint8_t *p){ |
121 | return util_sys_inb(base_addr+UART_IIR, p);
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122 | } |
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123 | 252 | up20180642 | |
124 | static int uart_enable_divisor_latch(int base_addr){ |
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125 | int ret = SUCCESS;
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126 | uint8_t conf; if((ret = uart_get_lcr(base_addr, &conf))) return ret; |
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127 | return uart_set_lcr(base_addr, conf | UART_DLAB);
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128 | } |
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129 | static int uart_disable_divisor_latch(int base_addr){ |
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130 | int ret = SUCCESS;
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131 | uint8_t conf; if((ret = uart_get_lcr(base_addr, &conf))) return ret; |
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132 | return uart_set_lcr(base_addr, conf & (~UART_DLAB));
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133 | } |
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134 | |||
135 | static int uart_get_ier(int base_addr, uint8_t *p){ |
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136 | int ret;
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137 | if((ret = uart_disable_divisor_latch(base_addr))) return ret; |
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138 | return util_sys_inb(base_addr+UART_IER, p);
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139 | } |
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140 | static int uart_set_ier(int base_addr, uint8_t n){ |
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141 | int ret;
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142 | if((ret = uart_disable_divisor_latch(base_addr))) return ret; |
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143 | if(sys_outb(base_addr+UART_IER, n)) return WRITE_ERROR; |
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144 | return SUCCESS;
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145 | } |
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146 | |||
147 | 235 | up20180642 | int uart_get_config(int base_addr, uart_config *config){ |
148 | int ret = SUCCESS;
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149 | |||
150 | config->base_addr = base_addr; |
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151 | |||
152 | 252 | up20180642 | if((ret = uart_get_lcr(base_addr, &config->lcr))) return ret; |
153 | 235 | up20180642 | |
154 | 252 | up20180642 | if((ret = uart_get_ier(base_addr, &config->ier))) return ret; |
155 | 242 | up20180642 | |
156 | if((ret = uart_enable_divisor_latch (base_addr))) return ret; |
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157 | 235 | up20180642 | if((ret = util_sys_inb(base_addr+UART_DLL, &config->dll ))) return ret; |
158 | if((ret = util_sys_inb(base_addr+UART_DLM, &config->dlm ))) return ret; |
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159 | 242 | up20180642 | if((ret = uart_disable_divisor_latch(base_addr))) return ret; |
160 | 235 | up20180642 | |
161 | uart_parse_config(config); |
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162 | return ret;
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163 | } |
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164 | void uart_print_config(uart_config config){
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165 | 249 | up20180642 | |
166 | printf("%s configuration:\n", (config.base_addr == COM1_ADDR ? "COM1" : "COM2")); |
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167 | printf("\tLCR = 0x%X: %d bits per char\t %d stop bits\t", config.lcr, config.bits_per_char, config.stop_bits);
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168 | if((config.parity&BIT(0)) == 0) printf("NO parity\n"); |
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169 | 235 | up20180642 | else switch(config.parity){ |
170 | 249 | up20180642 | case uart_parity_odd : printf("ODD parity\n" ); break; |
171 | case uart_parity_even: printf("EVEN parity\n" ); break; |
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172 | 235 | up20180642 | case uart_parity_par1: printf("parity bit is 1\n"); break; |
173 | case uart_parity_par0: printf("parity bit is 0\n"); break; |
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174 | default : printf("invalid\n" ); break; |
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175 | } |
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176 | 249 | up20180642 | printf("\tDLM = 0x%02X DLL=0x%02X: bitrate = %d bps\n", config.dlm, config.dll, UART_BITRATE/config.divisor_latch);
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177 | printf("\tIER = 0x%02X: Rx interrupts: %s\tTx interrupts: %s\n", config.ier,
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178 | (config.received_data_int ? "ENABLED":"DISABLED"), |
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179 | (config.transmitter_empty_int ? "ENABLED":"DISABLED")); |
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180 | 235 | up20180642 | } |
181 | |||
182 | int uart_set_bits_per_character(int base_addr, uint8_t bits_per_char){ |
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183 | if(bits_per_char < 5 || bits_per_char > 8) return INVALID_ARG; |
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184 | int ret = SUCCESS;
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185 | bits_per_char = (bits_per_char-5)&0x3; |
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186 | 252 | up20180642 | uint8_t conf; if((ret = uart_get_lcr(base_addr, &conf))) return ret; |
187 | 235 | up20180642 | conf = (conf & (~UART_BITS_PER_CHAR)) | bits_per_char; |
188 | 252 | up20180642 | return uart_set_lcr(base_addr, conf);
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189 | 235 | up20180642 | } |
190 | int uart_set_stop_bits(int base_addr, uint8_t stop){ |
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191 | if(stop != 1 && stop != 2) return INVALID_ARG; |
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192 | int ret = SUCCESS;
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193 | stop -= 1;
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194 | stop = (stop&1)<<2; |
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195 | 252 | up20180642 | uint8_t conf; if((ret = uart_get_lcr(base_addr, &conf))) return ret; |
196 | 235 | up20180642 | conf = (conf & (~UART_STOP_BITS)) | stop; |
197 | 252 | up20180642 | return uart_set_lcr(base_addr, conf);
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198 | 235 | up20180642 | } |
199 | int uart_set_parity(int base_addr, uart_parity par){ |
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200 | int ret = SUCCESS;
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201 | uint8_t parity = par << 3;
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202 | 252 | up20180642 | uint8_t conf; if((ret = uart_get_lcr(base_addr, &conf))) return ret; |
203 | 235 | up20180642 | conf = (conf & (~UART_PARITY)) | parity; |
204 | 252 | up20180642 | return uart_set_lcr(base_addr, conf);
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205 | 235 | up20180642 | } |
206 | 241 | up20180642 | int uart_set_bit_rate(int base_addr, float bit_rate){ |
207 | 235 | up20180642 | int ret = SUCCESS;
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208 | uint16_t latch = UART_BITRATE/bit_rate; |
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209 | 241 | up20180642 | uint8_t dll = UART_GET_DLL(latch); |
210 | uint8_t dlm = UART_GET_DLM(latch); |
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211 | 235 | up20180642 | if((ret = uart_enable_divisor_latch(base_addr))) return ret; |
212 | if(sys_outb(base_addr+UART_DLL, dll)) return WRITE_ERROR; |
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213 | if(sys_outb(base_addr+UART_DLM, dlm)) return WRITE_ERROR; |
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214 | 249 | up20180642 | if((ret = uart_disable_divisor_latch(base_addr))) return ret; |
215 | 235 | up20180642 | return SUCCESS;
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216 | } |
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217 | 249 | up20180642 | |
218 | 252 | up20180642 | static int uart_get_char(int base_addr, uint8_t *p){ |
219 | 249 | up20180642 | int ret;
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220 | if((ret = uart_disable_divisor_latch(base_addr))) return ret; |
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221 | return util_sys_inb(base_addr+UART_RBR, p);
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222 | } |
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223 | 252 | up20180642 | static int uart_send_char(int base_addr, uint8_t c){ |
224 | 249 | up20180642 | int ret;
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225 | if((ret = uart_disable_divisor_latch(base_addr))) return ret; |
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226 | 252 | up20180642 | if(sys_outb(base_addr+UART_THR, c)) return WRITE_ERROR; |
227 | 249 | up20180642 | return SUCCESS;
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228 | } |
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229 | 252 | up20180642 | static int uart_receiver_ready(int base_addr){ |
230 | 249 | up20180642 | uint8_t lsr; |
231 | if(uart_get_lsr(base_addr, &lsr)) return false; |
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232 | return UART_GET_RECEIVER_READY(lsr);
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233 | } |
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234 | 252 | up20180642 | static int uart_transmitter_empty(int base_addr){ |
235 | 249 | up20180642 | uint8_t lsr; |
236 | if(uart_get_lsr(base_addr, &lsr)) return false; |
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237 | return UART_GET_TRANSMITTER_EMPTY(lsr);
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238 | } |
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239 | 252 | up20180642 | |
240 | int uart_enable_int_rx(int base_addr){ |
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241 | int ret;
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242 | uint8_t ier; |
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243 | if((ret = uart_get_ier(base_addr, &ier))) return ret; |
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244 | ier |= UART_INT_EN_RX; |
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245 | return uart_set_ier(base_addr, ier);
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246 | } |
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247 | int uart_disable_int_rx(int base_addr){ |
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248 | int ret;
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249 | uint8_t ier; |
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250 | if((ret = uart_get_ier(base_addr, &ier))) return ret; |
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251 | ier &= ~UART_INT_EN_RX; |
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252 | return uart_set_ier(base_addr, ier);
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253 | } |
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254 | int uart_enable_int_tx(int base_addr){ |
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255 | int ret;
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256 | uint8_t ier; |
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257 | if((ret = uart_get_ier(base_addr, &ier))) return ret; |
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258 | ier |= UART_INT_EN_TX; |
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259 | return uart_set_ier(base_addr, ier);
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260 | } |
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261 | int uart_disable_int_tx(int base_addr){ |
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262 | int ret;
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263 | uint8_t ier; |
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264 | if((ret = uart_get_ier(base_addr, &ier))) return ret; |
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265 | ier &= ~UART_INT_EN_TX; |
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266 | return uart_set_ier(base_addr, ier);
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267 | } |
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268 | |||
269 | 261 | up20180642 | #include "nctp.h" |
270 | |||
271 | #define NCTP_START 0x80 |
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272 | #define NCTP_END 0xFF |
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273 | #define NCTP_OK 0xFF |
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274 | #define NCTP_NOK 0x00 |
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275 | #define NCTP_MAX_SIZE 1024 //in bytes |
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276 | |||
277 | 275 | up20180642 | queue_t *out = NULL;
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278 | queue_t *in = NULL;
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279 | 261 | up20180642 | |
280 | 275 | up20180642 | int nctp_init(void){ |
281 | out = queue_ctor(); if(out == NULL) return NULL_PTR; |
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282 | in = queue_ctor(); if(in == NULL) return NULL_PTR; |
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283 | return SUCCESS;
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284 | 261 | up20180642 | } |
285 | 275 | up20180642 | int nctp_free(void){ |
286 | while(!queue_empty(out)){
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287 | free(queue_top(out)); |
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288 | queue_pop(out); |
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289 | 261 | up20180642 | } |
290 | 275 | up20180642 | while(!queue_empty(in)){
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291 | free(queue_top(in)); |
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292 | queue_pop(in); |
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293 | 261 | up20180642 | } |
294 | 275 | up20180642 | return SUCCESS;
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295 | 261 | up20180642 | } |
296 | |||
297 | 275 | up20180642 | int nctp_send(size_t num, uint8_t* ptr[], size_t sz[]){
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298 | 261 | up20180642 | { |
299 | int cnt = 0; |
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300 | for(size_t i = 0; i < num; ++i){ |
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301 | cnt += sz[i]; |
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302 | if(cnt > NCTP_MAX_SIZE) return TRANS_REFUSED; |
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303 | } |
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304 | } |
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305 | int ret;
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306 | 275 | up20180642 | uint8_t *tmp; |
307 | tmp = malloc(sizeof(uint8_t)); *tmp = NCTP_START; queue_push(out, tmp);
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308 | 261 | up20180642 | for(size_t i = 0; i < num; ++i){ |
309 | uint8_t *p = ptr[i]; size_t s = sz[i]; |
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310 | 275 | up20180642 | for(size_t j = 0; j < s; ++j, ++p){ |
311 | tmp = malloc(sizeof(uint8_t)); *tmp = *p; queue_push(out, tmp);
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312 | } |
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313 | 261 | up20180642 | } |
314 | 275 | up20180642 | tmp = malloc(sizeof(uint8_t)); *tmp = NCTP_END; queue_push(out, tmp);
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315 | if(uart_transmitter_empty(COM1_ADDR)){
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316 | if((ret = uart_send_char(COM1_ADDR, *(uint8_t*)queue_top(out)))) return ret; |
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317 | queue_pop(out); |
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318 | } |
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319 | 249 | up20180642 | return SUCCESS;
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320 | } |
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321 | 275 | up20180642 | |
322 | static int nctp_transmit(void){ |
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323 | if(!queue_empty(out)){
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324 | int ret = uart_send_char(COM1_ADDR, *(uint8_t*)queue_top(out));
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325 | queue_pop(out); |
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326 | return ret;
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327 | }else return SUCCESS; |
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328 | 269 | up20180642 | } |
329 | 275 | up20180642 | static void process(){ |
330 | free(queue_top(in)); queue_pop(in); |
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331 | while(*(uint8_t*)queue_top(in) != NCTP_END){
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332 | printf("%c", *(uint8_t*)queue_top(in));
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333 | free(queue_top(in)); queue_pop(in); |
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334 | } |
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335 | free(queue_top(in)); queue_pop(in); |
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336 | } |
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337 | static int nctp_receive(void){ |
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338 | 249 | up20180642 | int ret;
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339 | 261 | up20180642 | uint8_t c; |
340 | 275 | up20180642 | while(uart_receiver_ready(COM1_ADDR)){
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341 | if((ret = uart_get_char(COM1_ADDR, &c))) return ret; |
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342 | uint8_t *tmp = malloc(sizeof(uint8_t)); *tmp = c;
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343 | queue_push(in, tmp); |
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344 | if(c == NCTP_END) process();
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345 | 261 | up20180642 | } |
346 | 275 | up20180642 | return SUCCESS;
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347 | 249 | up20180642 | } |
348 | 275 | up20180642 | |
349 | int nctp_ih_err = SUCCESS;
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350 | void nctp_ih(void){ |
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351 | uint8_t iir; |
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352 | if((nctp_ih_err = uart_get_iir(COM1_ADDR, &iir))) return; |
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353 | if(UART_GET_IF_INT_PEND(iir)){
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354 | switch(UART_GET_INT_PEND(iir)){
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355 | case UART_INT_RX: nctp_receive (); break; |
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356 | case UART_INT_TX: nctp_transmit(); break; |
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357 | default: break; |
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358 | } |
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359 | } |
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360 | 269 | up20180642 | } |
361 | 275 | up20180642 | |
362 | /// HLTP
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363 | int hltp_send_string(const char *p){ |
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364 | uint8_t* ptr[1]; ptr[0] = (uint8_t*)p; |
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365 | size_t sz[1]; sz[0] = strlen(p)+1; |
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366 | return nctp_send(1, ptr, sz); |
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367 | } |