root / proj / src / uart.c @ 259
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| 1 | 235 | up20180642 | #include <lcom/lcf.h> |
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| 2 | |||
| 3 | #include "uart.h" |
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| 4 | |||
| 5 | #include "errors.h" |
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| 6 | |||
| 7 | 249 | up20180642 | #define UART_BITRATE 115200 |
| 8 | #define UART_WAIT 20 //microseconds |
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| 9 | 241 | up20180642 | |
| 10 | 249 | up20180642 | #define UART_RBR 0 |
| 11 | #define UART_THR 0 |
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| 12 | #define UART_IER 1 |
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| 13 | #define UART_IIR 2 |
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| 14 | #define UART_FCR 2 |
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| 15 | #define UART_LCR 3 |
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| 16 | #define UART_MCR 4 |
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| 17 | #define UART_LSR 5 |
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| 18 | #define UART_MSR 6 |
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| 19 | #define UART_SR 7 |
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| 20 | 241 | up20180642 | |
| 21 | 249 | up20180642 | #define UART_DLL 0 |
| 22 | #define UART_DLM 1 |
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| 23 | 241 | up20180642 | |
| 24 | 249 | up20180642 | /// LCR
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| 25 | #define UART_BITS_PER_CHAR_POS 0 |
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| 26 | #define UART_STOP_BITS_POS 2 |
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| 27 | #define UART_PARITY_POS 3 |
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| 28 | #define UART_BREAK_CONTROL_POS 6 |
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| 29 | #define UART_DLAB_POS 7 |
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| 30 | 241 | up20180642 | |
| 31 | 249 | up20180642 | #define UART_BITS_PER_CHAR (BIT(0) | BIT(1)) |
| 32 | #define UART_STOP_BITS (BIT(2)) |
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| 33 | #define UART_PARITY (BIT(3) | BIT(4) | BIT(5)) |
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| 34 | #define UART_BREAK_CONTROL (BIT(6)) |
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| 35 | #define UART_DLAB (BIT(7)) |
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| 36 | 241 | up20180642 | |
| 37 | 249 | up20180642 | #define UART_GET_BITS_PER_CHAR(n) (((n)&UART_BITS_PER_CHAR) + 5) |
| 38 | #define UART_GET_STOP_BITS(n) (((n)&UART_STOP_BITS)? 2 : 1) |
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| 39 | #define UART_GET_PARITY(n) (((n)&UART_PARITY )>>UART_PARITY_POS )
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| 40 | #define UART_GET_BREAK_CONTROL(n) (((n)&UART_BREAK_CONTROL)>>UART_BREAK_CONTROL_POS)
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| 41 | #define UART_GET_DLAB(n) (((n)&UART_DLAB )>>UART_DLAB_POS )
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| 42 | #define UART_GET_DIV_LATCH(m,l) ((m)<<8 | (l)) |
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| 43 | #define UART_GET_DLL(n) ((n)&0xFF) |
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| 44 | #define UART_GET_DLM(n) (((n)>>8)&0xFF) |
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| 45 | 242 | up20180642 | |
| 46 | 249 | up20180642 | /// IER
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| 47 | 252 | up20180642 | #define UART_INT_EN_RX_POS 0 |
| 48 | #define UART_INT_EN_TX_POS 1 |
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| 49 | 249 | up20180642 | #define UART_INT_EN_RECEIVER_LINE_STAT_POS 2 |
| 50 | #define UART_INT_EN_MODEM_STAT_POS 3 |
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| 51 | 242 | up20180642 | |
| 52 | 252 | up20180642 | #define UART_INT_EN_RX (BIT(0)) |
| 53 | #define UART_INT_EN_TX (BIT(1)) |
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| 54 | 249 | up20180642 | #define UART_INT_EN_RECEIVER_LINE_STAT (BIT(2)) |
| 55 | #define UART_INT_EN_MODEM_STAT (BIT(3)) |
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| 56 | 242 | up20180642 | |
| 57 | 252 | up20180642 | #define UART_GET_INT_EN_RX(n) (((n)&UART_INT_EN_RX )>>UART_INT_EN_RX_POS )
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| 58 | #define UART_GET_INT_EN_TX(n) (((n)&UART_INT_EN_TX )>>UART_INT_EN_TX_POS )
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| 59 | #define UART_GET_INT_EN_RECEIVER_LINE_STAT(n) (((n)&UART_INT_EN_RECEIVER_LINE_STAT)>>UART_INT_EN_RECEIVER_LINE_STAT_POS)
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| 60 | #define UART_GET_INT_EN_MODEM_STAT(n) (((n)&UART_INT_EN_MODEM_STAT )>>UART_INT_EN_MODEM_STAT_POS )
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| 61 | 249 | up20180642 | |
| 62 | /// LSR
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| 63 | #define UART_RECEIVER_READY_POS 0 |
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| 64 | #define UART_TRANSMITTER_EMPTY_POS 5 |
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| 65 | |||
| 66 | #define UART_RECEIVER_READY (BIT(0)) |
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| 67 | #define UART_TRANSMITTER_EMPTY (BIT(5)) |
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| 68 | |||
| 69 | #define UART_GET_RECEIVER_READY(n) (((n)&UART_RECEIVER_READY )>>UART_RECEIVER_READY_POS )
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| 70 | #define UART_GET_TRANSMITTER_EMPTY(n) (((n)&UART_TRANSMITTER_EMPTY )>>UART_TRANSMITTER_EMPTY_POS )
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| 71 | |||
| 72 | 252 | up20180642 | static void uart_parse_config(uart_config *config){ |
| 73 | /// LCR
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| 74 | config->bits_per_char = UART_GET_BITS_PER_CHAR (config->lcr); |
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| 75 | config->stop_bits = UART_GET_STOP_BITS (config->lcr); |
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| 76 | config->parity = UART_GET_PARITY (config->lcr); if((config->parity & BIT(0)) == 0) config->parity = uart_parity_none; |
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| 77 | config->break_control = UART_GET_BREAK_CONTROL (config->lcr); |
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| 78 | config->dlab = UART_GET_DLAB (config->lcr); |
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| 79 | /// IER
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| 80 | config->received_data_int = UART_GET_INT_EN_RX (config->ier); |
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| 81 | config->transmitter_empty_int = UART_GET_INT_EN_TX (config->ier); |
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| 82 | config->receiver_line_stat_int = UART_GET_INT_EN_RECEIVER_LINE_STAT(config->ier); |
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| 83 | config->modem_stat_int = UART_GET_INT_EN_MODEM_STAT (config->ier); |
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| 84 | /// DIV LATCH
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| 85 | config->divisor_latch = UART_GET_DIV_LATCH(config->dlm, config->dll); |
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| 86 | } |
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| 87 | |||
| 88 | static int uart_get_lcr(int base_addr, uint8_t *p){ |
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| 89 | return util_sys_inb(base_addr+UART_LCR, p);
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| 90 | } |
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| 91 | static int uart_set_lcr(int base_addr, uint8_t config){ |
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| 92 | if(sys_outb(base_addr+UART_LCR, config)) return WRITE_ERROR; |
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| 93 | return SUCCESS;
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| 94 | } |
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| 95 | static int uart_get_lsr(int base_addr, uint8_t *p){ |
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| 96 | return util_sys_inb(base_addr+UART_LSR, p);
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| 97 | } |
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| 98 | |||
| 99 | static int uart_enable_divisor_latch(int base_addr){ |
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| 100 | int ret = SUCCESS;
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| 101 | uint8_t conf; if((ret = uart_get_lcr(base_addr, &conf))) return ret; |
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| 102 | return uart_set_lcr(base_addr, conf | UART_DLAB);
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| 103 | } |
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| 104 | static int uart_disable_divisor_latch(int base_addr){ |
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| 105 | int ret = SUCCESS;
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| 106 | uint8_t conf; if((ret = uart_get_lcr(base_addr, &conf))) return ret; |
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| 107 | return uart_set_lcr(base_addr, conf & (~UART_DLAB));
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| 108 | } |
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| 109 | |||
| 110 | static int uart_get_ier(int base_addr, uint8_t *p){ |
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| 111 | int ret;
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| 112 | if((ret = uart_disable_divisor_latch(base_addr))) return ret; |
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| 113 | return util_sys_inb(base_addr+UART_IER, p);
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| 114 | } |
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| 115 | static int uart_set_ier(int base_addr, uint8_t n){ |
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| 116 | int ret;
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| 117 | if((ret = uart_disable_divisor_latch(base_addr))) return ret; |
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| 118 | if(sys_outb(base_addr+UART_IER, n)) return WRITE_ERROR; |
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| 119 | return SUCCESS;
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| 120 | } |
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| 121 | |||
| 122 | 235 | up20180642 | int uart_get_config(int base_addr, uart_config *config){ |
| 123 | int ret = SUCCESS;
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| 124 | |||
| 125 | config->base_addr = base_addr; |
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| 126 | |||
| 127 | 252 | up20180642 | if((ret = uart_get_lcr(base_addr, &config->lcr))) return ret; |
| 128 | 235 | up20180642 | |
| 129 | 252 | up20180642 | if((ret = uart_get_ier(base_addr, &config->ier))) return ret; |
| 130 | 242 | up20180642 | |
| 131 | if((ret = uart_enable_divisor_latch (base_addr))) return ret; |
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| 132 | 235 | up20180642 | if((ret = util_sys_inb(base_addr+UART_DLL, &config->dll ))) return ret; |
| 133 | if((ret = util_sys_inb(base_addr+UART_DLM, &config->dlm ))) return ret; |
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| 134 | 242 | up20180642 | if((ret = uart_disable_divisor_latch(base_addr))) return ret; |
| 135 | 235 | up20180642 | |
| 136 | uart_parse_config(config); |
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| 137 | return ret;
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| 138 | } |
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| 139 | void uart_print_config(uart_config config){
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| 140 | 249 | up20180642 | |
| 141 | printf("%s configuration:\n", (config.base_addr == COM1_ADDR ? "COM1" : "COM2")); |
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| 142 | printf("\tLCR = 0x%X: %d bits per char\t %d stop bits\t", config.lcr, config.bits_per_char, config.stop_bits);
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| 143 | if((config.parity&BIT(0)) == 0) printf("NO parity\n"); |
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| 144 | 235 | up20180642 | else switch(config.parity){ |
| 145 | 249 | up20180642 | case uart_parity_odd : printf("ODD parity\n" ); break; |
| 146 | case uart_parity_even: printf("EVEN parity\n" ); break; |
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| 147 | 235 | up20180642 | case uart_parity_par1: printf("parity bit is 1\n"); break; |
| 148 | case uart_parity_par0: printf("parity bit is 0\n"); break; |
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| 149 | default : printf("invalid\n" ); break; |
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| 150 | } |
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| 151 | 249 | up20180642 | printf("\tDLM = 0x%02X DLL=0x%02X: bitrate = %d bps\n", config.dlm, config.dll, UART_BITRATE/config.divisor_latch);
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| 152 | printf("\tIER = 0x%02X: Rx interrupts: %s\tTx interrupts: %s\n", config.ier,
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| 153 | (config.received_data_int ? "ENABLED":"DISABLED"), |
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| 154 | (config.transmitter_empty_int ? "ENABLED":"DISABLED")); |
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| 155 | 235 | up20180642 | } |
| 156 | |||
| 157 | int uart_set_bits_per_character(int base_addr, uint8_t bits_per_char){ |
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| 158 | if(bits_per_char < 5 || bits_per_char > 8) return INVALID_ARG; |
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| 159 | int ret = SUCCESS;
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| 160 | bits_per_char = (bits_per_char-5)&0x3; |
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| 161 | 252 | up20180642 | uint8_t conf; if((ret = uart_get_lcr(base_addr, &conf))) return ret; |
| 162 | 235 | up20180642 | conf = (conf & (~UART_BITS_PER_CHAR)) | bits_per_char; |
| 163 | 252 | up20180642 | return uart_set_lcr(base_addr, conf);
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| 164 | 235 | up20180642 | } |
| 165 | int uart_set_stop_bits(int base_addr, uint8_t stop){ |
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| 166 | if(stop != 1 && stop != 2) return INVALID_ARG; |
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| 167 | int ret = SUCCESS;
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| 168 | stop -= 1;
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| 169 | stop = (stop&1)<<2; |
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| 170 | 252 | up20180642 | uint8_t conf; if((ret = uart_get_lcr(base_addr, &conf))) return ret; |
| 171 | 235 | up20180642 | conf = (conf & (~UART_STOP_BITS)) | stop; |
| 172 | 252 | up20180642 | return uart_set_lcr(base_addr, conf);
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| 173 | 235 | up20180642 | } |
| 174 | int uart_set_parity(int base_addr, uart_parity par){ |
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| 175 | int ret = SUCCESS;
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| 176 | uint8_t parity = par << 3;
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| 177 | 252 | up20180642 | uint8_t conf; if((ret = uart_get_lcr(base_addr, &conf))) return ret; |
| 178 | 235 | up20180642 | conf = (conf & (~UART_PARITY)) | parity; |
| 179 | 252 | up20180642 | return uart_set_lcr(base_addr, conf);
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| 180 | 235 | up20180642 | } |
| 181 | 241 | up20180642 | int uart_set_bit_rate(int base_addr, float bit_rate){ |
| 182 | 235 | up20180642 | int ret = SUCCESS;
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| 183 | uint16_t latch = UART_BITRATE/bit_rate; |
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| 184 | 241 | up20180642 | uint8_t dll = UART_GET_DLL(latch); |
| 185 | uint8_t dlm = UART_GET_DLM(latch); |
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| 186 | 235 | up20180642 | if((ret = uart_enable_divisor_latch(base_addr))) return ret; |
| 187 | if(sys_outb(base_addr+UART_DLL, dll)) return WRITE_ERROR; |
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| 188 | if(sys_outb(base_addr+UART_DLM, dlm)) return WRITE_ERROR; |
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| 189 | 249 | up20180642 | if((ret = uart_disable_divisor_latch(base_addr))) return ret; |
| 190 | 235 | up20180642 | return SUCCESS;
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| 191 | } |
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| 192 | 249 | up20180642 | |
| 193 | 252 | up20180642 | static int uart_get_char(int base_addr, uint8_t *p){ |
| 194 | 249 | up20180642 | int ret;
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| 195 | if((ret = uart_disable_divisor_latch(base_addr))) return ret; |
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| 196 | return util_sys_inb(base_addr+UART_RBR, p);
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| 197 | } |
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| 198 | 252 | up20180642 | static int uart_send_char(int base_addr, uint8_t c){ |
| 199 | 249 | up20180642 | int ret;
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| 200 | if((ret = uart_disable_divisor_latch(base_addr))) return ret; |
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| 201 | 252 | up20180642 | if(sys_outb(base_addr+UART_THR, c)) return WRITE_ERROR; |
| 202 | 249 | up20180642 | return SUCCESS;
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| 203 | } |
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| 204 | 252 | up20180642 | static int uart_receiver_ready(int base_addr){ |
| 205 | 249 | up20180642 | uint8_t lsr; |
| 206 | if(uart_get_lsr(base_addr, &lsr)) return false; |
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| 207 | return UART_GET_RECEIVER_READY(lsr);
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| 208 | } |
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| 209 | 252 | up20180642 | static int uart_transmitter_empty(int base_addr){ |
| 210 | 249 | up20180642 | uint8_t lsr; |
| 211 | if(uart_get_lsr(base_addr, &lsr)) return false; |
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| 212 | return UART_GET_TRANSMITTER_EMPTY(lsr);
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| 213 | } |
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| 214 | 252 | up20180642 | |
| 215 | int uart_enable_int_rx(int base_addr){ |
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| 216 | int ret;
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| 217 | uint8_t ier; |
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| 218 | if((ret = uart_get_ier(base_addr, &ier))) return ret; |
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| 219 | ier |= UART_INT_EN_RX; |
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| 220 | return uart_set_ier(base_addr, ier);
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| 221 | } |
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| 222 | int uart_disable_int_rx(int base_addr){ |
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| 223 | int ret;
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| 224 | uint8_t ier; |
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| 225 | if((ret = uart_get_ier(base_addr, &ier))) return ret; |
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| 226 | ier &= ~UART_INT_EN_RX; |
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| 227 | return uart_set_ier(base_addr, ier);
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| 228 | } |
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| 229 | int uart_enable_int_tx(int base_addr){ |
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| 230 | int ret;
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| 231 | uint8_t ier; |
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| 232 | if((ret = uart_get_ier(base_addr, &ier))) return ret; |
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| 233 | ier |= UART_INT_EN_TX; |
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| 234 | return uart_set_ier(base_addr, ier);
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| 235 | } |
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| 236 | int uart_disable_int_tx(int base_addr){ |
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| 237 | int ret;
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| 238 | uint8_t ier; |
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| 239 | if((ret = uart_get_ier(base_addr, &ier))) return ret; |
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| 240 | ier &= ~UART_INT_EN_TX; |
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| 241 | return uart_set_ier(base_addr, ier);
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| 242 | } |
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| 243 | |||
| 244 | 249 | up20180642 | int uart_get_char_poll(int base_addr, uint8_t *p){ |
| 245 | int ret;
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| 246 | while(!uart_receiver_ready(base_addr)){}
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| 247 | if((ret = uart_get_char(base_addr, p))) return ret; |
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| 248 | return SUCCESS;
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| 249 | } |
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| 250 | int uart_send_char_poll(int base_addr, uint8_t c){ |
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| 251 | int ret;
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| 252 | while(!uart_transmitter_empty(base_addr)){}
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| 253 | if((ret = uart_send_char(base_addr, c))) return ret; |
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| 254 | return SUCCESS;
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| 255 | } |