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| 1 | 13 | up20180614 | /* $NetBSD: cacheinfo.h,v 1.19 2014/09/09 15:11:33 msaitoh Exp $ */
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| 2 | |||
| 3 | #ifndef _X86_CACHEINFO_H_
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| 4 | #define _X86_CACHEINFO_H_
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| 5 | |||
| 6 | struct x86_cache_info {
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| 7 | uint8_t cai_index; |
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| 8 | uint8_t cai_desc; |
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| 9 | uint8_t cai_associativity; |
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| 10 | u_int cai_totalsize; /* #entries for TLB, bytes for cache */
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| 11 | u_int cai_linesize; /*
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| 12 | * or page size for TLB,
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| 13 | * or prefetch size
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| 14 | */
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| 15 | #ifndef _KERNEL
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| 16 | const char *cai_string; |
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| 17 | #endif
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| 18 | }; |
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| 19 | |||
| 20 | #define CAI_ITLB 0 /* Instruction TLB (4K pages) */ |
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| 21 | #define CAI_ITLB2 1 /* Instruction TLB (2/4M pages) */ |
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| 22 | #define CAI_DTLB 2 /* Data TLB (4K pages) */ |
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| 23 | #define CAI_DTLB2 3 /* Data TLB (2/4M pages) */ |
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| 24 | #define CAI_ICACHE 4 /* Instruction cache */ |
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| 25 | #define CAI_DCACHE 5 /* Data cache */ |
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| 26 | #define CAI_L2CACHE 6 /* Level 2 cache */ |
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| 27 | #define CAI_L3CACHE 7 /* Level 3 cache */ |
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| 28 | #define CAI_L1_1GBITLB 8 /* L1 1GB Page instruction TLB */ |
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| 29 | #define CAI_L1_1GBDTLB 9 /* L1 1GB Page data TLB */ |
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| 30 | #define CAI_L2_1GBITLB 10 /* L2 1GB Page instruction TLB */ |
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| 31 | #define CAI_L2_1GBDTLB 11 /* L2 1GB Page data TLB */ |
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| 32 | #define CAI_L2_ITLB 12 /* L2 Instruction TLB (4K pages) */ |
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| 33 | #define CAI_L2_ITLB2 13 /* L2 Instruction TLB (2/4M pages) */ |
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| 34 | #define CAI_L2_DTLB 14 /* L2 Data TLB (4K pages) */ |
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| 35 | #define CAI_L2_DTLB2 15 /* L2 Data TLB (2/4M pages) */ |
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| 36 | #define CAI_L2_STLB 16 /* Shared L2 TLB (4K pages) */ |
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| 37 | #define CAI_L2_STLB2 17 /* Shared L2 TLB (4K/2M pages) */ |
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| 38 | #define CAI_PREFETCH 18 /* Prefetch */ |
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| 39 | |||
| 40 | #define CAI_COUNT 19 |
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| 41 | |||
| 42 | /*
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| 43 | * AMD Cache Info:
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| 44 | *
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| 45 | * Barcelona, Phenom:
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| 46 | *
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| 47 | * Function 8000.0005 L1 TLB/Cache Information
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| 48 | * EAX -- L1 TLB 2/4MB pages
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| 49 | * EBX -- L1 TLB 4K pages
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| 50 | * ECX -- L1 D-cache
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| 51 | * EDX -- L1 I-cache
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| 52 | *
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| 53 | * Function 8000.0006 L2 TLB/Cache Information
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| 54 | * EAX -- L2 TLB 2/4MB pages
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| 55 | * EBX -- L2 TLB 4K pages
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| 56 | * ECX -- L2 Unified cache
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| 57 | * EDX -- L3 Unified Cache
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| 58 | *
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| 59 | * Function 8000.0019 TLB 1GB Page Information
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| 60 | * EAX -- L1 1GB pages
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| 61 | * EBX -- L2 1GB pages
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| 62 | * ECX -- reserved
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| 63 | * EDX -- reserved
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| 64 | *
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| 65 | * Athlon, Duron:
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| 66 | *
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| 67 | * Function 8000.0005 L1 TLB/Cache Information
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| 68 | * EAX -- L1 TLB 2/4MB pages
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| 69 | * EBX -- L1 TLB 4K pages
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| 70 | * ECX -- L1 D-cache
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| 71 | * EDX -- L1 I-cache
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| 72 | *
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| 73 | * Function 8000.0006 L2 TLB/Cache Information
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| 74 | * EAX -- L2 TLB 2/4MB pages
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| 75 | * EBX -- L2 TLB 4K pages
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| 76 | * ECX -- L2 Unified cache
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| 77 | * EDX -- reserved
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| 78 | *
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| 79 | * K5, K6:
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| 80 | *
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| 81 | * Function 8000.0005 L1 TLB/Cache Information
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| 82 | * EAX -- reserved
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| 83 | * EBX -- TLB 4K pages
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| 84 | * ECX -- L1 D-cache
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| 85 | * EDX -- L1 I-cache
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| 86 | *
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| 87 | * K6-III:
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| 88 | *
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| 89 | * Function 8000.0006 L2 Cache Information
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| 90 | * EAX -- reserved
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| 91 | * EBX -- reserved
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| 92 | * ECX -- L2 Unified cache
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| 93 | * EDX -- reserved
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| 94 | */
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| 95 | |||
| 96 | /* L1 TLB 2/4MB pages */
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| 97 | #define AMD_L1_EAX_DTLB_ASSOC(x) (((x) >> 24) & 0xff) |
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| 98 | #define AMD_L1_EAX_DTLB_ENTRIES(x) (((x) >> 16) & 0xff) |
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| 99 | #define AMD_L1_EAX_ITLB_ASSOC(x) (((x) >> 8) & 0xff) |
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| 100 | #define AMD_L1_EAX_ITLB_ENTRIES(x) ( (x) & 0xff) |
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| 101 | |||
| 102 | /* L1 TLB 4K pages */
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| 103 | #define AMD_L1_EBX_DTLB_ASSOC(x) (((x) >> 24) & 0xff) |
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| 104 | #define AMD_L1_EBX_DTLB_ENTRIES(x) (((x) >> 16) & 0xff) |
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| 105 | #define AMD_L1_EBX_ITLB_ASSOC(x) (((x) >> 8) & 0xff) |
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| 106 | #define AMD_L1_EBX_ITLB_ENTRIES(x) ( (x) & 0xff) |
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| 107 | |||
| 108 | /* L1 Data Cache */
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| 109 | #define AMD_L1_ECX_DC_SIZE(x) ((((x) >> 24) & 0xff) * 1024) |
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| 110 | #define AMD_L1_ECX_DC_ASSOC(x) (((x) >> 16) & 0xff) |
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| 111 | #define AMD_L1_ECX_DC_LPT(x) (((x) >> 8) & 0xff) |
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| 112 | #define AMD_L1_ECX_DC_LS(x) ( (x) & 0xff) |
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| 113 | |||
| 114 | /* L1 Instruction Cache */
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| 115 | #define AMD_L1_EDX_IC_SIZE(x) ((((x) >> 24) & 0xff) * 1024) |
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| 116 | #define AMD_L1_EDX_IC_ASSOC(x) (((x) >> 16) & 0xff) |
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| 117 | #define AMD_L1_EDX_IC_LPT(x) (((x) >> 8) & 0xff) |
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| 118 | #define AMD_L1_EDX_IC_LS(x) ( (x) & 0xff) |
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| 119 | |||
| 120 | /* Note for L2 TLB -- if the upper 16 bits are 0, it is a unified TLB */
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| 121 | |||
| 122 | /* L2 TLB 2/4MB pages */
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| 123 | #define AMD_L2_EAX_DTLB_ASSOC(x) (((x) >> 28) & 0xf) |
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| 124 | #define AMD_L2_EAX_DTLB_ENTRIES(x) (((x) >> 16) & 0xfff) |
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| 125 | #define AMD_L2_EAX_IUTLB_ASSOC(x) (((x) >> 12) & 0xf) |
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| 126 | #define AMD_L2_EAX_IUTLB_ENTRIES(x) ( (x) & 0xfff) |
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| 127 | |||
| 128 | /* L2 TLB 4K pages */
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| 129 | #define AMD_L2_EBX_DTLB_ASSOC(x) (((x) >> 28) & 0xf) |
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| 130 | #define AMD_L2_EBX_DTLB_ENTRIES(x) (((x) >> 16) & 0xfff) |
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| 131 | #define AMD_L2_EBX_IUTLB_ASSOC(x) (((x) >> 12) & 0xf) |
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| 132 | #define AMD_L2_EBX_IUTLB_ENTRIES(x) ( (x) & 0xfff) |
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| 133 | |||
| 134 | /* L2 Cache */
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| 135 | #define AMD_L2_ECX_C_SIZE(x) ((((x) >> 16) & 0xffff) * 1024) |
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| 136 | #define AMD_L2_ECX_C_ASSOC(x) (((x) >> 12) & 0xf) |
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| 137 | #define AMD_L2_ECX_C_LPT(x) (((x) >> 8) & 0xf) |
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| 138 | #define AMD_L2_ECX_C_LS(x) ( (x) & 0xff) |
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| 139 | |||
| 140 | /* L3 Cache */
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| 141 | #define AMD_L3_EDX_C_SIZE(x) ((((x) >> 18) & 0xffff) * 1024 * 512) |
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| 142 | #define AMD_L3_EDX_C_ASSOC(x) (((x) >> 12) & 0xff) |
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| 143 | #define AMD_L3_EDX_C_LPT(x) (((x) >> 8) & 0xf) |
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| 144 | #define AMD_L3_EDX_C_LS(x) ( (x) & 0xff) |
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| 145 | |||
| 146 | /* L1 TLB 1GB pages */
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| 147 | #define AMD_L1_1GB_EAX_DTLB_ASSOC(x) (((x) >> 28) & 0xf) |
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| 148 | #define AMD_L1_1GB_EAX_DTLB_ENTRIES(x) (((x) >> 16) & 0xfff) |
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| 149 | #define AMD_L1_1GB_EAX_IUTLB_ASSOC(x) (((x) >> 12) & 0xf) |
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| 150 | #define AMD_L1_1GB_EAX_IUTLB_ENTRIES(x) ( (x) & 0xfff) |
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| 151 | |||
| 152 | /* L2 TLB 1GB pages */
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| 153 | #define AMD_L2_1GB_EBX_DUTLB_ASSOC(x) (((x) >> 28) & 0xf) |
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| 154 | #define AMD_L2_1GB_EBX_DUTLB_ENTRIES(x) (((x) >> 16) & 0xfff) |
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| 155 | #define AMD_L2_1GB_EBX_IUTLB_ASSOC(x) (((x) >> 12) & 0xf) |
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| 156 | #define AMD_L2_1GB_EBX_IUTLB_ENTRIES(x) ( (x) & 0xfff) |
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| 157 | |||
| 158 | /*
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| 159 | * VIA Cache Info:
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| 160 | *
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| 161 | * Nehemiah (at least)
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| 162 | *
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| 163 | * Function 8000.0005 L1 TLB/Cache Information
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| 164 | * EAX -- reserved
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| 165 | * EBX -- L1 TLB 4K pages
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| 166 | * ECX -- L1 D-cache
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| 167 | * EDX -- L1 I-cache
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| 168 | *
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| 169 | * Function 8000.0006 L2 Cache Information
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| 170 | * EAX -- reserved
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| 171 | * EBX -- reserved
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| 172 | * ECX -- L2 Unified cache
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| 173 | * EDX -- reserved
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| 174 | */
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| 175 | |||
| 176 | /* L1 TLB 4K pages */
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| 177 | #define VIA_L1_EBX_DTLB_ASSOC(x) (((x) >> 24) & 0xff) |
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| 178 | #define VIA_L1_EBX_DTLB_ENTRIES(x) (((x) >> 16) & 0xff) |
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| 179 | #define VIA_L1_EBX_ITLB_ASSOC(x) (((x) >> 8) & 0xff) |
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| 180 | #define VIA_L1_EBX_ITLB_ENTRIES(x) ( (x) & 0xff) |
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| 181 | |||
| 182 | /* L1 Data Cache */
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| 183 | #define VIA_L1_ECX_DC_SIZE(x) ((((x) >> 24) & 0xff) * 1024) |
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| 184 | #define VIA_L1_ECX_DC_ASSOC(x) (((x) >> 16) & 0xff) |
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| 185 | #define VIA_L1_ECX_DC_LPT(x) (((x) >> 8) & 0xff) |
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| 186 | #define VIA_L1_ECX_DC_LS(x) ( (x) & 0xff) |
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| 187 | |||
| 188 | /* L1 Instruction Cache */
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| 189 | #define VIA_L1_EDX_IC_SIZE(x) ((((x) >> 24) & 0xff) * 1024) |
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| 190 | #define VIA_L1_EDX_IC_ASSOC(x) (((x) >> 16) & 0xff) |
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| 191 | #define VIA_L1_EDX_IC_LPT(x) (((x) >> 8) & 0xff) |
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| 192 | #define VIA_L1_EDX_IC_LS(x) ( (x) & 0xff) |
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| 193 | |||
| 194 | /* L2 Cache (pre-Nehemiah) */
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| 195 | #define VIA_L2_ECX_C_SIZE(x) ((((x) >> 24) & 0xff) * 1024) |
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| 196 | #define VIA_L2_ECX_C_ASSOC(x) (((x) >> 16) & 0xff) |
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| 197 | #define VIA_L2_ECX_C_LPT(x) (((x) >> 8) & 0xff) |
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| 198 | #define VIA_L2_ECX_C_LS(x) ( (x) & 0xff) |
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| 199 | |||
| 200 | /* L2 Cache (Nehemiah and newer) */
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| 201 | #define VIA_L2N_ECX_C_SIZE(x) ((((x) >> 16) & 0xffff) * 1024) |
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| 202 | #define VIA_L2N_ECX_C_ASSOC(x) (((x) >> 12) & 0xf) |
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| 203 | #define VIA_L2N_ECX_C_LPT(x) (((x) >> 8) & 0xf) |
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| 204 | #define VIA_L2N_ECX_C_LS(x) ( (x) & 0xff) |
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| 205 | |||
| 206 | #ifdef _KERNEL
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| 207 | #define __CI_TBL(a,b,c,d,e,f) { a, b, c, d, e }
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| 208 | #else
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| 209 | #define __CI_TBL(a,b,c,d,e,f) { a, b, c, d, e, f }
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| 210 | #endif
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| 211 | |||
| 212 | /*
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| 213 | * XXX Currently organized mostly by cache type, but would be
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| 214 | * XXX easier to maintain if it were in descriptor type order.
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| 215 | */
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| 216 | #define INTEL_CACHE_INFO { \
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| 217 | __CI_TBL(CAI_ITLB, 0x01, 4, 32, 4 * 1024, NULL), \ |
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| 218 | __CI_TBL(CAI_ITLB2, 0x02, 0xff, 2, 4 * 1024 * 1024, NULL), \ |
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| 219 | __CI_TBL(CAI_DTLB, 0x03, 4, 64, 4 * 1024, NULL), \ |
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| 220 | __CI_TBL(CAI_DTLB2, 0x04, 4, 8, 4 * 1024 * 1024, NULL), \ |
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| 221 | __CI_TBL(CAI_DTLB2, 0x05, 4, 32, 4 * 1024 * 1024, NULL), \ |
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| 222 | __CI_TBL(CAI_ITLB2, 0x0b, 4, 4, 4 * 1024 * 1024, NULL), \ |
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| 223 | __CI_TBL(CAI_ITLB, 0x4f, 0xff, 32, 4 * 1024, NULL), \ |
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| 224 | __CI_TBL(CAI_ITLB, 0x50, 0xff, 64, 4 * 1024, "4K/4M: 64 entries"), \ |
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| 225 | __CI_TBL(CAI_ITLB, 0x51, 0xff, 64, 4 * 1024, "4K/4M: 128 entries"),\ |
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| 226 | __CI_TBL(CAI_ITLB, 0x52, 0xff, 64, 4 * 1024, "4K/4M: 256 entries"),\ |
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| 227 | __CI_TBL(CAI_ITLB2, 0x55, 0xff, 64, 4 * 1024, "2M/4M: 7 entries"), \ |
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| 228 | __CI_TBL(CAI_DTLB2, 0x56, 4, 16, 4 * 1024 * 1024, NULL), \ |
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| 229 | __CI_TBL(CAI_DTLB, 0x57, 4, 16, 4 * 1024, NULL), \ |
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| 230 | __CI_TBL(CAI_DTLB, 0x59, 0xff, 16, 4 * 1024, NULL), \ |
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| 231 | __CI_TBL(CAI_DTLB2, 0x5a, 0xff, 64, 4 * 1024, "2M/4M: 32 entries (L0)"), \ |
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| 232 | __CI_TBL(CAI_DTLB, 0x5b, 0xff, 64, 4 * 1024, "4K/4M: 64 entries"), \ |
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| 233 | __CI_TBL(CAI_DTLB, 0x5c, 0xff, 64, 4 * 1024, "4K/4M: 128 entries"),\ |
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| 234 | __CI_TBL(CAI_DTLB, 0x5d, 0xff, 64, 4 * 1024, "4K/4M: 256 entries"),\ |
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| 235 | __CI_TBL(CAI_ITLB, 0x61, 0xff, 48, 4 * 1024, NULL), \ |
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| 236 | __CI_TBL(CAI_L1_1GBDTLB,0x63, 4, 4,1024*1024 * 1024, NULL), \ |
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| 237 | __CI_TBL(CAI_ITLB2, 0x76, 0xff, 8, 4 * 1024 * 1024, "2M/4M: 8 entries"), \ |
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| 238 | __CI_TBL(CAI_DTLB, 0xa0, 0xff, 32, 4 * 1024, NULL), \ |
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| 239 | __CI_TBL(CAI_ITLB, 0xb0, 4,128, 4 * 1024, NULL), \ |
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| 240 | __CI_TBL(CAI_ITLB2, 0xb1, 4, 64, 0, "8 2M/4 4M entries"), \ |
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| 241 | __CI_TBL(CAI_ITLB, 0xb2, 4, 64, 4 * 1024, NULL), \ |
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| 242 | __CI_TBL(CAI_DTLB, 0xb3, 4,128, 4 * 1024, NULL), \ |
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| 243 | __CI_TBL(CAI_DTLB, 0xb4, 4,256, 4 * 1024, NULL), \ |
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| 244 | __CI_TBL(CAI_ITLB, 0xb5, 8, 64, 4 * 1024, NULL), \ |
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| 245 | __CI_TBL(CAI_ITLB, 0xb6, 8,128, 4 * 1024, NULL), \ |
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| 246 | __CI_TBL(CAI_DTLB, 0xba, 4, 64, 4 * 1024, NULL), \ |
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| 247 | __CI_TBL(CAI_DTLB2, 0xc0, 4, 8, 4 * 1024, "4K/4M: 8 entries"), \ |
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| 248 | __CI_TBL(CAI_L2_STLB2, 0xc1, 8,1024, 4 * 1024, "4K/2M: 1024 entries"), \ |
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| 249 | __CI_TBL(CAI_DTLB2, 0xc2, 4, 16, 4 * 1024, "4K/2M: 16 entries"), \ |
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| 250 | __CI_TBL(CAI_L2_STLB, 0xc3, 6,1536, 4 * 1024, NULL), \ |
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| 251 | __CI_TBL(CAI_L2_STLB, 0xca, 4,512, 4 * 1024, NULL), \ |
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| 252 | __CI_TBL(CAI_ICACHE, 0x06, 4, 8 * 1024, 32, NULL), \ |
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| 253 | __CI_TBL(CAI_ICACHE, 0x08, 4, 16 * 1024, 32, NULL), \ |
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| 254 | __CI_TBL(CAI_ICACHE, 0x09, 4, 32 * 1024, 64, NULL), \ |
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| 255 | __CI_TBL(CAI_DCACHE, 0x0a, 2, 8 * 1024, 32, NULL), \ |
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| 256 | __CI_TBL(CAI_DCACHE, 0x0c, 4, 16 * 1024, 32, NULL), \ |
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| 257 | __CI_TBL(CAI_DCACHE, 0x0d, 4, 16 * 1024, 64, NULL), \ |
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| 258 | __CI_TBL(CAI_DCACHE, 0x0e, 6, 24 * 1024, 64, NULL), \ |
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| 259 | __CI_TBL(CAI_L2CACHE, 0x21, 8, 256 * 1024, 64, NULL), /* L2 (MLC) */ \ |
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| 260 | __CI_TBL(CAI_L3CACHE, 0x22, 0xff, 512 * 1024, 64, "sectored, 4-way "), \ |
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| 261 | __CI_TBL(CAI_L3CACHE, 0x23, 0xff, 1 * 1024 * 1024, 64, "sectored, 8-way "), \ |
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| 262 | __CI_TBL(CAI_L2CACHE, 0x24, 16, 1 * 1024 * 1024, 64, NULL), \ |
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| 263 | __CI_TBL(CAI_L3CACHE, 0x25, 0xff, 2 * 1024 * 1024, 64, "sectored, 8-way "), \ |
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| 264 | __CI_TBL(CAI_L3CACHE, 0x29, 0xff, 4 * 1024 * 1024, 64, "sectored, 8-way "), \ |
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| 265 | __CI_TBL(CAI_DCACHE, 0x2c, 8, 32 * 1024, 64, NULL), \ |
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| 266 | __CI_TBL(CAI_ICACHE, 0x30, 8, 32 * 1024, 64, NULL), \ |
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| 267 | __CI_TBL(CAI_L2CACHE, 0x39, 4, 128 * 1024, 64, NULL), \ |
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| 268 | __CI_TBL(CAI_L2CACHE, 0x3a, 6, 192 * 1024, 64, NULL), \ |
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| 269 | __CI_TBL(CAI_L2CACHE, 0x3b, 2, 128 * 1024, 64, NULL), \ |
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| 270 | __CI_TBL(CAI_L2CACHE, 0x3c, 4, 256 * 1024, 64, NULL), \ |
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| 271 | __CI_TBL(CAI_L2CACHE, 0x3d, 6, 384 * 1024, 64, NULL), \ |
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| 272 | __CI_TBL(CAI_L2CACHE, 0x3e, 4, 512 * 1024, 64, NULL), \ |
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| 273 | __CI_TBL(CAI_L2CACHE, 0x40, 0, 0, 0, "not present"), \ |
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| 274 | __CI_TBL(CAI_L2CACHE, 0x41, 4, 128 * 1024, 32, NULL), \ |
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| 275 | __CI_TBL(CAI_L2CACHE, 0x42, 4, 256 * 1024, 32, NULL), \ |
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| 276 | __CI_TBL(CAI_L2CACHE, 0x43, 4, 512 * 1024, 32, NULL), \ |
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| 277 | __CI_TBL(CAI_L2CACHE, 0x44, 4, 1 * 1024 * 1024, 32, NULL), \ |
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| 278 | __CI_TBL(CAI_L2CACHE, 0x45, 4, 2 * 1024 * 1024, 32, NULL), \ |
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| 279 | __CI_TBL(CAI_L3CACHE, 0x46, 4, 4 * 1024 * 1024, 64, NULL), \ |
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| 280 | __CI_TBL(CAI_L3CACHE, 0x47, 8, 8 * 1024 * 1024, 64, NULL), \ |
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| 281 | __CI_TBL(CAI_L2CACHE, 0x48, 12, 3 * 1024 * 1024, 64, NULL), \ |
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| 282 | \ |
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| 283 | /* 0x49 Is L2 on Xeon MP (Family 0f, Model 06), L3 otherwise */ \
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| 284 | __CI_TBL(CAI_L2CACHE, 0x49, 16, 4 * 1024 * 1024, 64, NULL), \ |
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| 285 | __CI_TBL(CAI_L3CACHE, 0x49, 16, 4 * 1024 * 1024, 64, NULL), \ |
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| 286 | __CI_TBL(CAI_L3CACHE, 0x4a, 12, 6 * 1024 * 1024, 64, NULL), \ |
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| 287 | __CI_TBL(CAI_L3CACHE, 0x4b, 16, 8 * 1024 * 1024, 64, NULL), \ |
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| 288 | __CI_TBL(CAI_L3CACHE, 0x4c, 12,12 * 1024 * 1024, 64, NULL), \ |
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| 289 | __CI_TBL(CAI_L3CACHE, 0x4d, 16,16 * 1024 * 1024, 64, NULL), \ |
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| 290 | __CI_TBL(CAI_L2CACHE, 0x4e, 24, 6 * 1024 * 1024, 64, NULL), \ |
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| 291 | __CI_TBL(CAI_DCACHE, 0x60, 8, 16 * 1024, 64, NULL), \ |
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| 292 | __CI_TBL(CAI_DCACHE, 0x66, 4, 8 * 1024, 64, NULL), \ |
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| 293 | __CI_TBL(CAI_DCACHE, 0x67, 4, 16 * 1024, 64, NULL), \ |
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| 294 | __CI_TBL(CAI_DCACHE, 0x68, 4, 32 * 1024, 64, NULL), \ |
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| 295 | __CI_TBL(CAI_ICACHE, 0x70, 8, 12 * 1024, 64, "12K uOp cache"), \ |
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| 296 | __CI_TBL(CAI_ICACHE, 0x71, 8, 16 * 1024, 64, "16K uOp cache"), \ |
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| 297 | __CI_TBL(CAI_ICACHE, 0x72, 8, 32 * 1024, 64, "32K uOp cache"), \ |
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| 298 | __CI_TBL(CAI_ICACHE, 0x73, 8, 64 * 1024, 64, "64K uOp cache"), \ |
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| 299 | __CI_TBL(CAI_L2CACHE, 0x78, 4, 1 * 1024 * 1024, 64, NULL), \ |
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| 300 | __CI_TBL(CAI_L2CACHE, 0x79, 8, 128 * 1024, 64, NULL), \ |
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| 301 | __CI_TBL(CAI_L2CACHE, 0x7a, 8, 256 * 1024, 64, NULL), \ |
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| 302 | __CI_TBL(CAI_L2CACHE, 0x7b, 8, 512 * 1024, 64, NULL), \ |
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| 303 | __CI_TBL(CAI_L2CACHE, 0x7c, 8, 1 * 1024 * 1024, 64, NULL), \ |
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| 304 | __CI_TBL(CAI_L2CACHE, 0x7d, 8, 2 * 1024 * 1024, 64, NULL), \ |
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| 305 | __CI_TBL(CAI_L2CACHE, 0x7f, 2, 512 * 1024, 64, NULL), \ |
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| 306 | __CI_TBL(CAI_L2CACHE, 0x80, 8, 512 * 1024, 64, NULL), \ |
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| 307 | __CI_TBL(CAI_L2CACHE, 0x82, 8, 256 * 1024, 32, NULL), \ |
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| 308 | __CI_TBL(CAI_L2CACHE, 0x83, 8, 512 * 1024, 32, NULL), \ |
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| 309 | __CI_TBL(CAI_L2CACHE, 0x84, 8, 1 * 1024 * 1024, 32, NULL), \ |
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| 310 | __CI_TBL(CAI_L2CACHE, 0x85, 8, 2 * 1024 * 1024, 32, NULL), \ |
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| 311 | __CI_TBL(CAI_L2CACHE, 0x86, 4, 512 * 1024, 64, NULL), \ |
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| 312 | __CI_TBL(CAI_L2CACHE, 0x87, 8, 1 * 1024 * 1024, 64, NULL), \ |
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| 313 | __CI_TBL(CAI_L3CACHE, 0xd0, 4, 512 * 1024, 64, NULL), \ |
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| 314 | __CI_TBL(CAI_L3CACHE, 0xd1, 4, 1 * 1024 * 1024, 64, NULL), \ |
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| 315 | __CI_TBL(CAI_L3CACHE, 0xd2, 4, 2 * 1024 * 1024, 64, NULL), \ |
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| 316 | __CI_TBL(CAI_L3CACHE, 0xd6, 8, 1 * 1024 * 1024, 64, NULL), \ |
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| 317 | __CI_TBL(CAI_L3CACHE, 0xd7, 8, 2 * 1024 * 1024, 64, NULL), \ |
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| 318 | __CI_TBL(CAI_L3CACHE, 0xd8, 8, 4 * 1024 * 1024, 64, NULL), \ |
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| 319 | __CI_TBL(CAI_L3CACHE, 0xdc, 12, 3 * 512 * 1024, 64, NULL), \ |
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| 320 | __CI_TBL(CAI_L3CACHE, 0xdd, 12, 3 * 1024 * 1024, 64, NULL), \ |
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| 321 | __CI_TBL(CAI_L3CACHE, 0xde, 12, 6 * 1024 * 1024, 64, NULL), \ |
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| 322 | __CI_TBL(CAI_L3CACHE, 0xe2, 16, 2 * 1024 * 1024, 64, NULL), \ |
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| 323 | __CI_TBL(CAI_L3CACHE, 0xe3, 16, 4 * 1024 * 1024, 64, NULL), \ |
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| 324 | __CI_TBL(CAI_L3CACHE, 0xe4, 16, 8 * 1024 * 1024, 64, NULL), \ |
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| 325 | __CI_TBL(CAI_L3CACHE, 0xea, 24,12 * 1024 * 1024, 64, NULL), \ |
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| 326 | __CI_TBL(CAI_L3CACHE, 0xeb, 24,18 * 1024 * 1024, 64, NULL), \ |
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| 327 | __CI_TBL(CAI_L3CACHE, 0xec, 24,24 * 1024 * 1024, 64, NULL), \ |
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| 328 | __CI_TBL(CAI_PREFETCH, 0xf0, 0, 0, 64, NULL), \ |
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| 329 | __CI_TBL(CAI_PREFETCH, 0xf1, 0, 0,128, NULL), \ |
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| 330 | /* 0xff means no cache information in CPUID leaf 2 (and use leaf 4) */ \
|
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| 331 | __CI_TBL(0, 0, 0, 0, 0, NULL) \ |
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| 332 | } |
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| 333 | |||
| 334 | #define AMD_L2CACHE_INFO { \
|
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| 335 | __CI_TBL(0, 0x01, 1, 0, 0, NULL), \ |
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| 336 | __CI_TBL(0, 0x02, 2, 0, 0, NULL), \ |
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| 337 | __CI_TBL(0, 0x04, 4, 0, 0, NULL), \ |
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| 338 | __CI_TBL(0, 0x06, 8, 0, 0, NULL), \ |
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| 339 | __CI_TBL(0, 0x08, 16, 0, 0, NULL), \ |
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| 340 | __CI_TBL(0, 0x0a, 32, 0, 0, NULL), \ |
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| 341 | __CI_TBL(0, 0x0b, 48, 0, 0, NULL), \ |
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| 342 | __CI_TBL(0, 0x0c, 64, 0, 0, NULL), \ |
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| 343 | __CI_TBL(0, 0x0d, 96, 0, 0, NULL), \ |
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| 344 | __CI_TBL(0, 0x0e, 128, 0, 0, NULL), \ |
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| 345 | __CI_TBL(0, 0x0f, 0xff, 0, 0, NULL), \ |
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| 346 | __CI_TBL(0, 0x00, 0, 0, 0, NULL) \ |
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| 347 | } |
||
| 348 | |||
| 349 | #define AMD_L3CACHE_INFO { \
|
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| 350 | __CI_TBL(0, 0x01, 1, 0, 0, NULL), \ |
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| 351 | __CI_TBL(0, 0x02, 2, 0, 0, NULL), \ |
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| 352 | __CI_TBL(0, 0x04, 4, 0, 0, NULL), \ |
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| 353 | __CI_TBL(0, 0x06, 8, 0, 0, NULL), \ |
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| 354 | __CI_TBL(0, 0x08, 16, 0, 0, NULL), \ |
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| 355 | __CI_TBL(0, 0x0a, 32, 0, 0, NULL), \ |
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| 356 | __CI_TBL(0, 0x0b, 48, 0, 0, NULL), \ |
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| 357 | __CI_TBL(0, 0x0c, 64, 0, 0, NULL), \ |
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| 358 | __CI_TBL(0, 0x0d, 96, 0, 0, NULL), \ |
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| 359 | __CI_TBL(0, 0x0e, 128, 0, 0, NULL), \ |
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| 360 | __CI_TBL(0, 0x0f, 0xff, 0, 0, NULL), \ |
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| 361 | __CI_TBL(0, 0x00, 0, 0, 0, NULL) \ |
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| 362 | } |
||
| 363 | |||
| 364 | #endif /* _X86_CACHEINFO_H_ */ |