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| 1 | 13 | up20180614 | /* $NetBSD: tgareg.h,v 1.6 2005/12/11 12:22:50 christos Exp $ */
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| 2 | |||
| 3 | /*
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| 4 | * Copyright (c) 1995, 1996 Carnegie-Mellon University.
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| 5 | * All rights reserved.
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| 6 | *
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| 7 | * Author: Chris G. Demetriou
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| 8 | *
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| 9 | * Permission to use, copy, modify and distribute this software and
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| 10 | * its documentation is hereby granted, provided that both the copyright
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| 11 | * notice and this permission notice appear in all copies of the
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| 12 | * software, derivative works or modified versions, and any portions
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| 13 | * thereof, and that both notices appear in supporting documentation.
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| 14 | *
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| 15 | * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
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| 16 | * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
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| 17 | * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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| 18 | *
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| 19 | * Carnegie Mellon requests users of this software to return to
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| 20 | *
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| 21 | * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
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| 22 | * School of Computer Science
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| 23 | * Carnegie Mellon University
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| 24 | * Pittsburgh PA 15213-3890
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| 25 | *
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| 26 | * any improvements or extensions that they make and grant Carnegie the
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| 27 | * rights to redistribute these changes.
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| 28 | */
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| 29 | |||
| 30 | #ifndef _ALPHA_INCLUDE_TGAREG_H_
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| 31 | #define _ALPHA_INCLUDE_TGAREG_H_
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| 32 | |||
| 33 | /*
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| 34 | * Device-specific PCI register offsets and contents.
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| 35 | */
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| 36 | |||
| 37 | #define TGA_PCIREG_PVRR 0x40 /* PCI Address Extension Register */ |
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| 38 | |||
| 39 | #define TGA_PCIREG_PAER 0x44 /* PCI VGA Redirect Register */ |
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| 40 | |||
| 41 | /*
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| 42 | * TGA Memory Space offsets
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| 43 | */
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| 44 | |||
| 45 | #define TGA_MEM_ALTROM 0x0000000 /* 0MB -- Alternate ROM space */ |
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| 46 | #define TGA2_MEM_EXTDEV 0x0000000 /* 0MB -- External Device Access */ |
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| 47 | #define TGA_MEM_CREGS 0x0100000 /* 1MB -- Core Registers */ |
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| 48 | #define TGA_CREGS_SIZE 0x0100000 /* Core registers occupy 1MB */ |
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| 49 | #define TGA_CREGS_ALIAS 0x0000400 /* Register copies every 1kB */ |
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| 50 | |||
| 51 | #define TGA2_MEM_CLOCK 0x0060000 /* TGA2 Clock access */ |
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| 52 | #define TGA2_MEM_RAMDAC 0x0080000 /* TGA2 RAMDAC access */ |
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| 53 | |||
| 54 | /* Display and Back Buffers mapped at config-dependent addresses */
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| 55 | |||
| 56 | /*
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| 57 | * TGA Core Space register numbers and contents.
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| 58 | */
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| 59 | |||
| 60 | typedef u_int32_t tga_reg_t;
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| 61 | |||
| 62 | #define TGA_REG_GCBR0 0x000 /* Copy buffer 0 */ |
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| 63 | #define TGA_REG_GCBR1 0x001 /* Copy buffer 1 */ |
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| 64 | #define TGA_REG_GCBR2 0x002 /* Copy buffer 2 */ |
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| 65 | #define TGA_REG_GCBR3 0x003 /* Copy buffer 3 */ |
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| 66 | #define TGA_REG_GCBR4 0x004 /* Copy buffer 4 */ |
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| 67 | #define TGA_REG_GCBR5 0x005 /* Copy buffer 5 */ |
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| 68 | #define TGA_REG_GCBR6 0x006 /* Copy buffer 6 */ |
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| 69 | #define TGA_REG_GCBR7 0x007 /* Copy buffer 7 */ |
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| 70 | |||
| 71 | #define TGA_REG_GFGR 0x008 /* Foreground */ |
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| 72 | #define TGA_REG_GBGR 0x009 /* Background */ |
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| 73 | #define TGA_REG_GPMR 0x00a /* Plane Mask */ |
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| 74 | #define TGA_REG_GPXR_S 0x00b /* Pixel Mask (one-shot) */ |
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| 75 | #define TGA_REG_GMOR 0x00c /* Mode */ |
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| 76 | #define TGA_REG_GOPR 0x00d /* Raster Operation */ |
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| 77 | #define TGA_REG_GPSR 0x00e /* Pixel Shift */ |
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| 78 | #define TGA_REG_GADR 0x00f /* Address */ |
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| 79 | |||
| 80 | #define TGA_REG_GB1R 0x010 /* Bresenham 1 */ |
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| 81 | #define TGA_REG_GB2R 0x011 /* Bresenham 2 */ |
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| 82 | #define TGA_REG_GB3R 0x012 /* Bresenham 3 */ |
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| 83 | |||
| 84 | #define TGA_REG_GCTR 0x013 /* Continue */ |
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| 85 | #define TGA_REG_GDER 0x014 /* Deep */ |
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| 86 | #define TGA_REG_GREV 0x015 /* Start/Version on TGA, |
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| 87 | * Revision on TGA2 */
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| 88 | #define TGA_REG_GSMR 0x016 /* Stencil Mode */ |
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| 89 | #define TGA_REG_GPXR_P 0x017 /* Pixel Mask (persistent) */ |
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| 90 | #define TGA_REG_CCBR 0x018 /* Cursor Base Address */ |
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| 91 | #define TGA_REG_VHCR 0x019 /* Horizontal Control */ |
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| 92 | #define TGA_REG_VVCR 0x01a /* Vertical Control */ |
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| 93 | #define TGA_REG_VVBR 0x01b /* Video Base Address */ |
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| 94 | #define TGA_REG_VVVR 0x01c /* Video Valid */ |
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| 95 | #define TGA_REG_CXYR 0x01d /* Cursor XY */ |
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| 96 | #define TGA_REG_VSAR 0x01e /* Video Shift Address */ |
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| 97 | #define TGA_REG_SISR 0x01f /* Interrupt Status */ |
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| 98 | #define TGA_REG_GDAR 0x020 /* Data */ |
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| 99 | #define TGA_REG_GRIR 0x021 /* Red Increment */ |
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| 100 | #define TGA_REG_GGIR 0x022 /* Green Increment */ |
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| 101 | #define TGA_REG_GBIR 0x023 /* Blue Increment */ |
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| 102 | #define TGA_REG_GZIR_L 0x024 /* Z-increment Low */ |
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| 103 | #define TGA_REG_GZIR_H 0x025 /* Z-Increment High */ |
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| 104 | #define TGA_REG_GDBR 0x026 /* DMA Base Address */ |
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| 105 | #define TGA_REG_GBWR 0x027 /* Bresenham Width */ |
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| 106 | #define TGA_REG_GZVR_L 0x028 /* Z-value Low */ |
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| 107 | #define TGA_REG_GZVR_H 0x029 /* Z-value High */ |
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| 108 | #define TGA_REG_GZBR 0x02a /* Z-base address */ |
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| 109 | /* GADR alias 0x02b */
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| 110 | #define TGA_REG_GRVR 0x02c /* Red Value */ |
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| 111 | #define TGA_REG_GGVR 0x02d /* Green Value */ |
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| 112 | #define TGA_REG_GBVR 0x02e /* Blue Value */ |
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| 113 | #define TGA_REG_GSWR 0x02f /* Span Width */ |
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| 114 | #define TGA_REG_EPSR 0x030 /* Pallete and DAC Setup */ |
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| 115 | |||
| 116 | /* reserved 0x031 - 0x3f */
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| 117 | |||
| 118 | #define TGA_REG_GSNR0 0x040 /* Slope-no-go 0 */ |
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| 119 | #define TGA_REG_GSNR1 0x041 /* Slope-no-go 1 */ |
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| 120 | #define TGA_REG_GSNR2 0x042 /* Slope-no-go 2 */ |
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| 121 | #define TGA_REG_GSNR3 0x043 /* Slope-no-go 3 */ |
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| 122 | #define TGA_REG_GSNR4 0x044 /* Slope-no-go 4 */ |
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| 123 | #define TGA_REG_GSNR5 0x045 /* Slope-no-go 5 */ |
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| 124 | #define TGA_REG_GSNR6 0x046 /* Slope-no-go 6 */ |
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| 125 | #define TGA_REG_GSNR7 0x047 /* Slope-no-go 7 */ |
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| 126 | |||
| 127 | #define TGA_REG_GSLR0 0x048 /* Slope 0 */ |
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| 128 | #define TGA_REG_GSLR1 0x049 /* Slope 1 */ |
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| 129 | #define TGA_REG_GSLR2 0x04a /* Slope 2 */ |
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| 130 | #define TGA_REG_GSLR3 0x04b /* Slope 3 */ |
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| 131 | #define TGA_REG_GSLR4 0x04c /* Slope 4 */ |
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| 132 | #define TGA_REG_GSLR5 0x04d /* Slope 5 */ |
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| 133 | #define TGA_REG_GSLR6 0x04e /* Slope 6 */ |
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| 134 | #define TGA_REG_GSLR7 0x04f /* Slope 7 */ |
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| 135 | |||
| 136 | #define TGA_REG_GBCR0 0x050 /* Block Color 0 */ |
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| 137 | #define TGA_REG_GBCR1 0x051 /* Block Color 1 */ |
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| 138 | #define TGA_REG_GBCR2 0x052 /* Block Color 2 */ |
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| 139 | #define TGA_REG_GBCR3 0x053 /* Block Color 3 */ |
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| 140 | #define TGA_REG_GBCR4 0x054 /* Block Color 4 */ |
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| 141 | #define TGA_REG_GBCR5 0x055 /* Block Color 5 */ |
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| 142 | #define TGA_REG_GBCR6 0x056 /* Block Color 6 */ |
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| 143 | #define TGA_REG_GBCR7 0x057 /* Block Color 7 */ |
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| 144 | |||
| 145 | #define TGA_REG_GCSR 0x058 /* Copy 64 Source */ |
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| 146 | #define TGA_REG_GCDR 0x059 /* Copy 64 Destination */ |
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| 147 | /* GC[SD]R aliases 0x05a - 0x05f */
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| 148 | |||
| 149 | /* reserved 0x060 - 0x077 */
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| 150 | |||
| 151 | #define TGA_REG_ERWR 0x078 /* EEPROM write */ |
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| 152 | |||
| 153 | /* reserved 0x079 */
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| 154 | |||
| 155 | #define TGA_REG_ECGR 0x07a /* Clock */ |
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| 156 | |||
| 157 | /* reserved 0x07b */
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| 158 | |||
| 159 | #define TGA_REG_EPDR 0x07c /* Pallete and DAC Data */ |
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| 160 | |||
| 161 | /* reserved 0x07d */
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| 162 | |||
| 163 | #define TGA_REG_SCSR 0x07e /* Command Status */ |
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| 164 | |||
| 165 | /* reserved 0x07f */
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| 166 | |||
| 167 | /*
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| 168 | * Video Valid Register
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| 169 | */
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| 170 | #define VVR_VIDEOVALID 0x00000001 /* 0 VGA, 1 TGA2 (TGA2 only) */ |
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| 171 | #define VVR_BLANK 0x00000002 /* 0 active, 1 blank */ |
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| 172 | #define VVR_CURSOR 0x00000004 /* 0 disable, 1 enable (TGA2 R/O) */ |
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| 173 | #define VVR_INTERLACE 0x00000008 /* 0 N/Int, 1 Int. (TGA2 R/O) */ |
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| 174 | #define VVR_DPMS_MASK 0x00000030 /* See "DMPS mask" below */ |
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| 175 | #define VVR_DPMS_SHIFT 4 |
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| 176 | #define VVR_DDC 0x00000040 /* DDC-in pin value (R/O) */ |
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| 177 | #define VVR_TILED 0x00000400 /* 0 linear, 1 tiled (not on TGA2) */ |
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| 178 | #define VVR_LDDLY_MASK 0x01ff0000 /* load delay in quad pixel clock ticks |
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| 179 | (not on TGA2) */
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| 180 | #define VVR_LDDLY_SHIFT 16 |
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| 181 | |||
| 182 | #endif /* _ALPHA_INCLUDE_TGAREG_H_ */ |